misc.isa (9554:406fbcf60223) misc.isa (10037:5cac77888310)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2012 ARM Limited
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 19 unchanged lines hidden (view full) ---

31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39// Giacomo Gabrielli
39
40
41def format ArmERet() {{
42 decode_block = "return new Eret(machInst);"
43}};
44
40def format Svc() {{
45def format Svc() {{
41 decode_block = "return new Svc(machInst);"
46 decode_block = "return new Svc(machInst, bits(machInst, 23, 0));"
42}};
43
47}};
48
49def format ArmSmcHyp() {{
50 decode_block = '''
51 {
52 if (bits(machInst, 21))
53 {
54 return new Smc(machInst);
55 } else {
56 uint32_t imm16 = (bits(machInst, 19, 8) << 4) |
57 (bits(machInst, 3, 0) << 0);
58 return new Hvc(machInst, imm16);
59 }
60 }
61 '''
62}};
63
44def format ArmMsrMrs() {{
45 decode_block = '''
46 {
47 const uint8_t byteMask = bits(machInst, 19, 16);
64def format ArmMsrMrs() {{
65 decode_block = '''
66 {
67 const uint8_t byteMask = bits(machInst, 19, 16);
68 const uint8_t sysM = byteMask | (bits(machInst, 8) << 4);
48 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
49 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
50 const uint32_t opcode = bits(machInst, 24, 21);
51 const bool useImm = bits(machInst, 25);
69 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
70 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
71 const uint32_t opcode = bits(machInst, 24, 21);
72 const bool useImm = bits(machInst, 25);
73 const bool r = bits(machInst, 22);
74 const bool isBanked = bits(machInst, 9);
52
53 const uint32_t unrotated = bits(machInst, 7, 0);
54 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
55 const uint32_t imm = rotate_imm(unrotated, rotation);
56
57 switch (opcode) {
58 case 0x8:
75
76 const uint32_t unrotated = bits(machInst, 7, 0);
77 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
78 const uint32_t imm = rotate_imm(unrotated, rotation);
79
80 switch (opcode) {
81 case 0x8:
59 return new MrsCpsr(machInst, rd);
82 if (isBanked) {
83 return new MrsBankedReg(machInst, rd, sysM, r!=0);
84 } else {
85 return new MrsCpsr(machInst, rd);
86 }
60 case 0x9:
61 if (useImm) {
62 return new MsrCpsrImm(machInst, imm, byteMask);
63 } else {
87 case 0x9:
88 if (useImm) {
89 return new MsrCpsrImm(machInst, imm, byteMask);
90 } else {
64 return new MsrCpsrReg(machInst, rn, byteMask);
91 if (isBanked) {
92 return new MsrBankedReg(machInst, rn, sysM, r!=0);
93 } else {
94 return new MsrCpsrReg(machInst, rn, byteMask);
95 }
65 }
66 case 0xa:
96 }
97 case 0xa:
67 return new MrsSpsr(machInst, rd);
98 if (isBanked) {
99 return new MrsBankedReg(machInst, rd, sysM, r!=0);
100 } else {
101 return new MrsSpsr(machInst, rd);
102 }
68 case 0xb:
69 if (useImm) {
70 return new MsrSpsrImm(machInst, imm, byteMask);
71 } else {
103 case 0xb:
104 if (useImm) {
105 return new MsrSpsrImm(machInst, imm, byteMask);
106 } else {
72 return new MsrSpsrReg(machInst, rn, byteMask);
107 if (isBanked) {
108 return new MsrBankedReg(machInst, rn, sysM, r!=0);
109 } else {
110 return new MsrSpsrReg(machInst, rn, byteMask);
111 }
73 }
74 default:
75 return new Unknown(machInst);
76 }
77 }
78 '''
79}};
80

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94 const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
95 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
96
97 const bool isRead = bits(machInst, 20);
98
99 switch (miscReg) {
100 case MISCREG_NOP:
101 return new NopInst(machInst);
112 }
113 default:
114 return new Unknown(machInst);
115 }
116 }
117 '''
118}};
119

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133 const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
134 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
135
136 const bool isRead = bits(machInst, 20);
137
138 switch (miscReg) {
139 case MISCREG_NOP:
140 return new NopInst(machInst);
102 case NUM_MISCREGS:
141 case MISCREG_CP14_UNIMPL:
103 return new FailUnimplemented(
104 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
105 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
106 machInst);
107 default:
142 return new FailUnimplemented(
143 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
144 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
145 machInst);
146 default:
147 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
108 if (isRead) {
148 if (isRead) {
109 return new Mrc14(machInst, rt, (IntRegIndex)miscReg);
149 return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss);
110 } else {
150 } else {
111 return new Mcr14(machInst, (IntRegIndex)miscReg, rt);
151 return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss);
112 }
113 }
114 }
115 '''
116}};
117
118def format McrMrc14() {{
119 decode_block = '''
120 return decodeMcrMrc14(machInst);
121 '''
122}};
123
124let {{
125 header_output = '''
152 }
153 }
154 }
155 '''
156}};
157
158def format McrMrc14() {{
159 decode_block = '''
160 return decodeMcrMrc14(machInst);
161 '''
162}};
163
164let {{
165 header_output = '''
126 StaticInstPtr
127 decodeMcrMrc15(ExtMachInst machInst);
166 StaticInstPtr decodeMcrMrc14(ExtMachInst machInst);
167 StaticInstPtr decodeMcrMrc15(ExtMachInst machInst);
128 '''
129 decoder_output = '''
130 StaticInstPtr
131 decodeMcrMrc15(ExtMachInst machInst)
132 {
133 const uint32_t opc1 = bits(machInst, 23, 21);
134 const uint32_t crn = bits(machInst, 19, 16);
135 const uint32_t opc2 = bits(machInst, 7, 5);
136 const uint32_t crm = bits(machInst, 3, 0);
137 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
138 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
168 '''
169 decoder_output = '''
170 StaticInstPtr
171 decodeMcrMrc15(ExtMachInst machInst)
172 {
173 const uint32_t opc1 = bits(machInst, 23, 21);
174 const uint32_t crn = bits(machInst, 19, 16);
175 const uint32_t opc2 = bits(machInst, 7, 5);
176 const uint32_t crm = bits(machInst, 3, 0);
177 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
178 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
139
140 const bool isRead = bits(machInst, 20);
179 const bool isRead = bits(machInst, 20);
180 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
141
142 switch (miscReg) {
143 case MISCREG_NOP:
144 return new NopInst(machInst);
181
182 switch (miscReg) {
183 case MISCREG_NOP:
184 return new NopInst(machInst);
145 case NUM_MISCREGS:
185 case MISCREG_CP15_UNIMPL:
146 return new FailUnimplemented(
147 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
148 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
149 machInst);
186 return new FailUnimplemented(
187 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
188 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
189 machInst);
150 case MISCREG_DCCISW:
151 return new WarnUnimplemented(
152 isRead ? "mrc dccisw" : "mcr dcisw", machInst);
153 case MISCREG_DCCIMVAC:
154 return new WarnUnimplemented(
155 isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
156 case MISCREG_DCIMVAC:
157 return new WarnUnimplemented(
158 isRead ? "mrc dcimvac" : "mcr dcimvac", machInst);
159 case MISCREG_DCCMVAC:
160 return new FlushPipeInst(
161 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
190 case MISCREG_DCCMVAC:
191 return new FlushPipeInst(
192 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
162 case MISCREG_DCCMVAU:
163 return new WarnUnimplemented(
164 isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
165 case MISCREG_CP15ISB:
193 case MISCREG_CP15ISB:
166 return new Isb(machInst);
194 return new Isb(machInst, iss);
167 case MISCREG_CP15DSB:
195 case MISCREG_CP15DSB:
168 return new Dsb(machInst);
196 return new Dsb(machInst, iss);
169 case MISCREG_CP15DMB:
197 case MISCREG_CP15DMB:
170 return new Dmb(machInst);
171 case MISCREG_ICIALLUIS:
172 return new WarnUnimplemented(
173 isRead ? "mrc icialluis" : "mcr icialluis", machInst);
174 case MISCREG_ICIMVAU:
175 return new WarnUnimplemented(
176 isRead ? "mrc icimvau" : "mcr icimvau", machInst);
177 case MISCREG_BPIMVA:
178 return new WarnUnimplemented(
179 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
180 case MISCREG_BPIALLIS:
181 return new WarnUnimplemented(
182 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
183 case MISCREG_BPIALL:
184 return new WarnUnimplemented(
185 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
186 case MISCREG_L2LATENCY:
187 return new WarnUnimplemented(
188 isRead ? "mrc l2latency" : "mcr l2latency", machInst);
189 case MISCREG_CRN15:
190 return new WarnUnimplemented(
191 isRead ? "mrc crn15" : "mcr crn15", machInst);
198 return new Dmb(machInst, iss);
199 default:
200 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
201 std::string full_mnem = csprintf("%s %s",
202 isRead ? "mrc" : "mcr", miscRegName[miscReg]);
203 warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
192
204
193 // Write only.
194 case MISCREG_TLBIALLIS:
195 case MISCREG_TLBIMVAIS:
196 case MISCREG_TLBIASIDIS:
197 case MISCREG_TLBIMVAAIS:
198 case MISCREG_ITLBIALL:
199 case MISCREG_ITLBIMVA:
200 case MISCREG_ITLBIASID:
201 case MISCREG_DTLBIALL:
202 case MISCREG_DTLBIMVA:
203 case MISCREG_DTLBIASID:
204 case MISCREG_TLBIALL:
205 case MISCREG_TLBIMVA:
206 case MISCREG_TLBIASID:
207 case MISCREG_TLBIMVAA:
208 if (isRead) {
209 return new Unknown(machInst);
210 } else {
211 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
205 // Remove the warn flag and set the implemented flag. This
206 // prevents the instruction warning a second time, it also
207 // means the instruction is actually generated. Actually
208 // creating the instruction to access an register that isn't
209 // implemented sounds a bit silly, but its required to get
210 // the correct behaviour for hyp traps and undef exceptions.
211 miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true;
212 miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
212 }
213
213 }
214
214 // Read only in user mode.
215 case MISCREG_TPIDRURO:
216 if (isRead) {
217 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
215 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
216 if (isRead)
217 return new Mrc15(machInst, rt, (IntRegIndex)miscReg, iss);
218 return new Mcr15(machInst, (IntRegIndex)miscReg, rt, iss);
218 } else {
219 } else {
219 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
220 return new FailUnimplemented(csprintf("%s %s",
221 isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
222 machInst);
220 }
223 }
224 }
225 }
226 '''
227}};
221
228
222 // Read/write in user mode.
223 case MISCREG_TPIDRURW:
224 if (isRead) {
225 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
226 } else {
227 return new Mcr15User(machInst, (IntRegIndex)miscReg, rt);
228 }
229def format McrMrc15() {{
230 decode_block = '''
231 return decodeMcrMrc15(machInst);
232 '''
233}};
229
234
230 // Read/write, priveleged only.
235let {{
236 header_output = '''
237 StaticInstPtr
238 decodeMcrrMrrc15(ExtMachInst machInst);
239 '''
240 decoder_output = '''
241 StaticInstPtr
242 decodeMcrrMrrc15(ExtMachInst machInst)
243 {
244 const uint32_t crm = bits(machInst, 3, 0);
245 const uint32_t opc1 = bits(machInst, 7, 4);
246 const MiscRegIndex miscReg = decodeCP15Reg64(crm, opc1);
247 const IntRegIndex rt = (IntRegIndex) (uint32_t) bits(machInst, 15, 12);
248 const IntRegIndex rt2 = (IntRegIndex) (uint32_t) bits(machInst, 19, 16);
249
250 const bool isRead = bits(machInst, 20);
251
252 switch (miscReg) {
253 case MISCREG_CP15_UNIMPL:
254 return new FailUnimplemented(
255 csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
256 crm, opc1, isRead ? "read" : "write").c_str(),
257 machInst);
231 default:
258 default:
232 if (miscReg >= MISCREG_CP15_UNIMP_START)
259 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
260 std::string full_mnem = csprintf("%s %s",
261 isRead ? "mrrc" : "mcrr", miscRegName[miscReg]);
262 warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
263
264 // Remove the warn flag and set the implemented flag. This
265 // prevents the instruction warning a second time, it also
266 // means the instruction is actually generated. Actually
267 // creating the instruction to access an register that isn't
268 // implemented sounds a bit silly, but its required to get
269 // the correct behaviour for hyp traps and undef exceptions.
270 miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true;
271 miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
272 }
273
274 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
275 uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
276
277 if (isRead)
278 return new Mrrc15(machInst, (IntRegIndex) miscReg, rt2, rt, iss);
279 return new Mcrr15(machInst, rt2, rt, (IntRegIndex) miscReg, iss);
280 } else {
233 return new FailUnimplemented(csprintf("%s %s",
281 return new FailUnimplemented(csprintf("%s %s",
234 isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
282 isRead ? "mrrc" : "mcrr", miscRegName[miscReg]).c_str(),
235 machInst);
283 machInst);
236 if (isRead) {
237 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
238 } else {
239 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
240 }
241 }
242 }
243 '''
244}};
245
284 }
285 }
286 }
287 '''
288}};
289
246def format McrMrc15() {{
290def format Mcrr15() {{
247 decode_block = '''
291 decode_block = '''
248 return decodeMcrMrc15(machInst);
292 return decodeMcrrMrrc15(machInst);
249 '''
250}};
293 '''
294}};
295
296def format Mrrc15() {{
297 decode_block = '''
298 return decodeMcrrMrrc15(machInst);
299 '''
300}};