misc.isa (7757:d7360f5052b2) misc.isa (7853:69aae4379062)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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95 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
96
97 const bool isRead = bits(machInst, 20);
98
99 switch (miscReg) {
100 case MISCREG_NOP:
101 return new NopInst(machInst);
102 case NUM_MISCREGS:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 86 unchanged lines hidden (view full) ---

95 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
96
97 const bool isRead = bits(machInst, 20);
98
99 switch (miscReg) {
100 case MISCREG_NOP:
101 return new NopInst(machInst);
102 case NUM_MISCREGS:
103 return new Unknown(machInst);
103 return new FailUnimplemented(
104 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
105 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
106 machInst);
104 case MISCREG_DCCISW:
105 return new WarnUnimplemented(
106 isRead ? "mrc dccisw" : "mcr dcisw", machInst);
107 case MISCREG_DCCIMVAC:
108 return new WarnUnimplemented(
109 isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
110 case MISCREG_DCIMVAC:
111 return new WarnUnimplemented(

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107 case MISCREG_DCCISW:
108 return new WarnUnimplemented(
109 isRead ? "mrc dccisw" : "mcr dcisw", machInst);
110 case MISCREG_DCCIMVAC:
111 return new WarnUnimplemented(
112 isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
113 case MISCREG_DCIMVAC:
114 return new WarnUnimplemented(

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