misc.isa (7404:bfc74724914e) misc.isa (7420:498b27bc326d)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 123 unchanged lines hidden (view full) ---

132 return new WarnUnimplemented(
133 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
134 case MISCREG_BPIALLIS:
135 return new WarnUnimplemented(
136 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
137 case MISCREG_BPIALL:
138 return new WarnUnimplemented(
139 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 123 unchanged lines hidden (view full) ---

132 return new WarnUnimplemented(
133 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
134 case MISCREG_BPIALLIS:
135 return new WarnUnimplemented(
136 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
137 case MISCREG_BPIALL:
138 return new WarnUnimplemented(
139 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
140
141 // Write only.
140 case MISCREG_TLBIALLIS:
141 case MISCREG_TLBIMVAIS:
142 case MISCREG_TLBIASIDIS:
143 case MISCREG_TLBIMVAAIS:
144 case MISCREG_ITLBIALL:
145 case MISCREG_ITLBIMVA:
146 case MISCREG_ITLBIASID:
147 case MISCREG_DTLBIALL:

--- 4 unchanged lines hidden (view full) ---

152 case MISCREG_TLBIASID:
153 case MISCREG_TLBIMVAA:
154 if (isRead) {
155 return new Unknown(machInst);
156 } else {
157 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
158 }
159
142 case MISCREG_TLBIALLIS:
143 case MISCREG_TLBIMVAIS:
144 case MISCREG_TLBIASIDIS:
145 case MISCREG_TLBIMVAAIS:
146 case MISCREG_ITLBIALL:
147 case MISCREG_ITLBIMVA:
148 case MISCREG_ITLBIASID:
149 case MISCREG_DTLBIALL:

--- 4 unchanged lines hidden (view full) ---

154 case MISCREG_TLBIASID:
155 case MISCREG_TLBIMVAA:
156 if (isRead) {
157 return new Unknown(machInst);
158 } else {
159 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
160 }
161
162 // Read only in user mode.
163 case MISCREG_TPIDRURO:
164 if (isRead) {
165 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
166 } else {
167 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
168 }
169
170 // Read/write in user mode.
171 case MISCREG_TPIDRURW:
172 if (isRead) {
173 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
174 } else {
175 return new Mcr15User(machInst, (IntRegIndex)miscReg, rt);
176 }
177
178 // Read/write, priveleged only.
160 default:
161 if (isRead) {
162 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
163 } else {
164 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
165 }
166 }
167 }
168 '''
169}};
170
171def format McrMrc15() {{
172 decode_block = '''
173 return decodeMcrMrc15(machInst);
174 '''
175}};
179 default:
180 if (isRead) {
181 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
182 } else {
183 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
184 }
185 }
186 }
187 '''
188}};
189
190def format McrMrc15() {{
191 decode_block = '''
192 return decodeMcrMrc15(machInst);
193 '''
194}};