misc.isa (7351:d90afcb8724e) misc.isa (7355:8d9b757b3583)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 114 unchanged lines hidden (view full) ---

123 return new WarnUnimplemented(
124 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
125 case MISCREG_BPIALLIS:
126 return new WarnUnimplemented(
127 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
128 case MISCREG_BPIALL:
129 return new WarnUnimplemented(
130 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 114 unchanged lines hidden (view full) ---

123 return new WarnUnimplemented(
124 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
125 case MISCREG_BPIALLIS:
126 return new WarnUnimplemented(
127 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
128 case MISCREG_BPIALL:
129 return new WarnUnimplemented(
130 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
131 case MISCREG_TLBIALLIS:
132 return new WarnUnimplemented(
133 isRead ? "mrc tlbiallis" : "mcr tlbiallis", machInst);
134 case MISCREG_TLBIMVAIS:
135 return new WarnUnimplemented(
136 isRead ? "mrc tlbimvais" : "mcr tlbimvais", machInst);
137 case MISCREG_TLBIASIDIS:
138 return new WarnUnimplemented(
139 isRead ? "mrc tlbiasidis" : "mcr tlbiasidis", machInst);
140 case MISCREG_TLBIMVAAIS:
141 return new WarnUnimplemented(
142 isRead ? "mrc tlbimvaais" : "mcr tlbimvaais", machInst);
143 case MISCREG_ITLBIALL:
144 return new WarnUnimplemented(
145 isRead ? "mrc itlbiall" : "mcr itlbiall", machInst);
146 case MISCREG_ITLBIMVA:
147 return new WarnUnimplemented(
148 isRead ? "mrc itlbimva" : "mcr itlbimva", machInst);
149 case MISCREG_ITLBIASID:
150 return new WarnUnimplemented(
151 isRead ? "mrc itlbiasid" : "mcr itlbiasid", machInst);
152 case MISCREG_DTLBIALL:
153 return new WarnUnimplemented(
154 isRead ? "mrc dtlbiall" : "mcr dtlbiall", machInst);
155 case MISCREG_DTLBIMVA:
156 return new WarnUnimplemented(
157 isRead ? "mrc dtlbimva" : "mcr dtlbimva", machInst);
158 case MISCREG_DTLBIASID:
159 return new WarnUnimplemented(
160 isRead ? "mrc dtlbiasid" : "mcr dtlbiasid", machInst);
161 case MISCREG_TLBIALL:
162 return new WarnUnimplemented(
163 isRead ? "mrc tlbiall" : "mcr tlbiall", machInst);
164 case MISCREG_TLBIMVA:
165 return new WarnUnimplemented(
166 isRead ? "mrc tlbimva" : "mcr tlbimva", machInst);
167 case MISCREG_TLBIASID:
168 return new WarnUnimplemented(
169 isRead ? "mrc tlbiasid" : "mcr tlbiasid", machInst);
170 case MISCREG_TLBIMVAA:
171 return new WarnUnimplemented(
172 isRead ? "mrc tlbimvaa" : "mcr tlbimvaa", machInst);
131 default:
132 if (isRead) {
133 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
134 } else {
135 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
136 }
137 }
138 }
139 '''
140}};
173 default:
174 if (isRead) {
175 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
176 } else {
177 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
178 }
179 }
180 }
181 '''
182}};