misc.isa (7297:2b127f2655d6) misc.isa (7300:3b491ad98fea)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 114 unchanged lines hidden (view full) ---

123 return new WarnUnimplemented(
124 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
125 case MISCREG_BPIALLIS:
126 return new WarnUnimplemented(
127 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
128 case MISCREG_BPIALL:
129 return new WarnUnimplemented(
130 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 114 unchanged lines hidden (view full) ---

123 return new WarnUnimplemented(
124 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
125 case MISCREG_BPIALLIS:
126 return new WarnUnimplemented(
127 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
128 case MISCREG_BPIALL:
129 return new WarnUnimplemented(
130 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
131 case MISCREG_DRBAR:
132 return new WarnUnimplemented(
133 isRead ? "mrc drbar" : "mcr drbar", machInst);
134 case MISCREG_DRACR:
135 return new WarnUnimplemented(
136 isRead ? "mrc dracr" : "mcr dracr", machInst);
137 case MISCREG_DRSR:
138 return new WarnUnimplemented(
139 isRead ? "mrc drsr" : "mcr drsr", machInst);
131 default:
132 if (isRead) {
133 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
134 } else {
135 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
136 }
137 }
138 }
139 '''
140}};
140 default:
141 if (isRead) {
142 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
143 } else {
144 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
145 }
146 }
147 }
148 '''
149}};