misc.isa (7264:fc3dfbfb3066) misc.isa (7267:fcbf902646a8)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 76 unchanged lines hidden (view full) ---

85 const uint32_t crn = bits(machInst, 19, 16);
86 const uint32_t opc2 = bits(machInst, 7, 5);
87 const uint32_t crm = bits(machInst, 3, 0);
88 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
89 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
90
91 const bool isRead = bits(machInst, 20);
92
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 76 unchanged lines hidden (view full) ---

85 const uint32_t crn = bits(machInst, 19, 16);
86 const uint32_t opc2 = bits(machInst, 7, 5);
87 const uint32_t crm = bits(machInst, 3, 0);
88 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
89 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
90
91 const bool isRead = bits(machInst, 20);
92
93 if (miscReg == MISCREG_NOP) {
93 switch (miscReg) {
94 case MISCREG_NOP:
94 return new NopInst(machInst);
95 return new NopInst(machInst);
95 } else if (miscReg == NUM_MISCREGS) {
96 case NUM_MISCREGS:
96 return new Unknown(machInst);
97 return new Unknown(machInst);
97 } else if (miscReg == MISCREG_DCCISW) {
98 return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw",
99 machInst);
100 } else {
98 case MISCREG_DCCISW:
99 return new WarnUnimplemented(
100 isRead ? "mrc dccisw" : "mcr dcisw", machInst);
101 case MISCREG_DCCIMVAC:
102 return new WarnUnimplemented(
103 isRead ? "mrc dccimvac" : "mcr dcimvac", machInst);
104 default:
101 if (isRead) {
102 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
103 } else {
104 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
105 }
106 }
107 }
108 '''
109}};
105 if (isRead) {
106 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
107 } else {
108 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
109 }
110 }
111 }
112 '''
113}};