| misc.isa (12258:08990d24fe41) | misc.isa (12358:386d26feb00f) |
|---|---|
| 1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
| 3// Copyright (c) 2010-2013,2016 ARM Limited | 3// Copyright (c) 2010-2013,2016-2017 ARM Limited |
| 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 202 unchanged lines hidden (view full) --- 214 case MISCREG_NOP: 215 return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop", 216 machInst, iss, MISCREG_NOP); 217 case MISCREG_CP15_UNIMPL: 218 return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown", 219 machInst, 220 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", 221 crn, opc1, crm, opc2, isRead ? "read" : "write")); | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 202 unchanged lines hidden (view full) --- 214 case MISCREG_NOP: 215 return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop", 216 machInst, iss, MISCREG_NOP); 217 case MISCREG_CP15_UNIMPL: 218 return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown", 219 machInst, 220 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", 221 crn, opc1, crm, opc2, isRead ? "read" : "write")); |
| 222 case MISCREG_DCCMVAC: 223 return new McrMrcMiscInst(isRead ? "mrc dccmvac" : "mcr dccmvac", 224 machInst, iss, MISCREG_DCCMVAC); | |
| 225 case MISCREG_CP15ISB: 226 return new Isb(machInst, iss); 227 case MISCREG_CP15DSB: 228 return new Dsb(machInst, iss); 229 case MISCREG_CP15DMB: 230 return new Dmb(machInst, iss); | 222 case MISCREG_CP15ISB: 223 return new Isb(machInst, iss); 224 case MISCREG_CP15DSB: 225 return new Dsb(machInst, iss); 226 case MISCREG_CP15DMB: 227 return new Dmb(machInst, iss); |
| 228 case MISCREG_DCIMVAC: 229 return new McrDcimvac(machInst, miscReg, rt, iss); 230 case MISCREG_DCCMVAC: 231 return new McrDccmvac(machInst, miscReg, rt, iss); 232 case MISCREG_DCCMVAU: 233 return new McrDccmvau(machInst, miscReg, rt, iss); 234 case MISCREG_DCCIMVAC: 235 return new McrDccimvac(machInst, miscReg, rt, iss); |
|
| 231 default: 232 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 233 std::string full_mnem = csprintf("%s %s", 234 isRead ? "mrc" : "mcr", miscRegName[miscReg]); 235 warn("\\tinstruction '%s' unimplemented\\n", full_mnem); 236 237 // Remove the warn flag and set the implemented flag. This 238 // prevents the instruction warning a second time, it also --- 97 unchanged lines hidden --- | 236 default: 237 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 238 std::string full_mnem = csprintf("%s %s", 239 isRead ? "mrc" : "mcr", miscRegName[miscReg]); 240 warn("\\tinstruction '%s' unimplemented\\n", full_mnem); 241 242 // Remove the warn flag and set the implemented flag. This 243 // prevents the instruction warning a second time, it also --- 97 unchanged lines hidden --- |