misc.isa (10506:aa23216161fa) misc.isa (11572:9eac6e12c673)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
3// Copyright (c) 2010-2013,2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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176 const uint32_t crm = bits(machInst, 3, 0);
177 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
178 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
179 const bool isRead = bits(machInst, 20);
180 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
181
182 switch (miscReg) {
183 case MISCREG_NOP:
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 164 unchanged lines hidden (view full) ---

176 const uint32_t crm = bits(machInst, 3, 0);
177 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
178 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
179 const bool isRead = bits(machInst, 20);
180 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
181
182 switch (miscReg) {
183 case MISCREG_NOP:
184 return new NopInst(machInst);
184 return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop",
185 machInst, iss, MISCREG_NOP);
185 case MISCREG_CP15_UNIMPL:
186 return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
187 machInst,
188 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
189 crn, opc1, crm, opc2, isRead ? "read" : "write"));
190 case MISCREG_DCCMVAC:
186 case MISCREG_CP15_UNIMPL:
187 return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
188 machInst,
189 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
190 crn, opc1, crm, opc2, isRead ? "read" : "write"));
191 case MISCREG_DCCMVAC:
191 return new FlushPipeInst(
192 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
192 return new McrMrcMiscInst(isRead ? "mrc dccmvac" : "mcr dccmvac",
193 machInst, iss, MISCREG_DCCMVAC);
193 case MISCREG_CP15ISB:
194 return new Isb(machInst, iss);
195 case MISCREG_CP15DSB:
196 return new Dsb(machInst, iss);
197 case MISCREG_CP15DMB:
198 return new Dmb(machInst, iss);
199 default:
200 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {

--- 103 unchanged lines hidden --- 		194 case MISCREG_CP15ISB:
195 return new Isb(machInst, iss);
196 case MISCREG_CP15DSB:
197 return new Dsb(machInst, iss);
198 case MISCREG_CP15DMB:
199 return new Dmb(machInst, iss);
200 default:
201 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {

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