misc.isa (10037:5cac77888310) misc.isa (10173:a6402a046e36)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 125 unchanged lines hidden (view full) ---

134 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
135
136 const bool isRead = bits(machInst, 20);
137
138 switch (miscReg) {
139 case MISCREG_NOP:
140 return new NopInst(machInst);
141 case MISCREG_CP14_UNIMPL:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 125 unchanged lines hidden (view full) ---

134 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
135
136 const bool isRead = bits(machInst, 20);
137
138 switch (miscReg) {
139 case MISCREG_NOP:
140 return new NopInst(machInst);
141 case MISCREG_CP14_UNIMPL:
142 return new FailUnimplemented(
142 return new FailUnimplemented(isRead ? "mrc unknown" : "mcr unknown",
143 machInst,
143 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
144 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
144 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
145 machInst);
145 crn, opc1, crm, opc2, isRead ? "read" : "write"));
146 default:
147 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
148 if (isRead) {
149 return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss);
150 } else {
151 return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss);
152 }
153 }

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178 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
179 const bool isRead = bits(machInst, 20);
180 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
181
182 switch (miscReg) {
183 case MISCREG_NOP:
184 return new NopInst(machInst);
185 case MISCREG_CP15_UNIMPL:
146 default:
147 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
148 if (isRead) {
149 return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss);
150 } else {
151 return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss);
152 }
153 }

--- 24 unchanged lines hidden (view full) ---

178 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
179 const bool isRead = bits(machInst, 20);
180 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
181
182 switch (miscReg) {
183 case MISCREG_NOP:
184 return new NopInst(machInst);
185 case MISCREG_CP15_UNIMPL:
186 return new FailUnimplemented(
186 return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
187 machInst,
187 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
188 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
188 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
189 machInst);
189 crn, opc1, crm, opc2, isRead ? "read" : "write"));
190 case MISCREG_DCCMVAC:
191 return new FlushPipeInst(
192 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
193 case MISCREG_CP15ISB:
194 return new Isb(machInst, iss);
195 case MISCREG_CP15DSB:
196 return new Dsb(machInst, iss);
197 case MISCREG_CP15DMB:

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212 miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
213 }
214
215 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
216 if (isRead)
217 return new Mrc15(machInst, rt, (IntRegIndex)miscReg, iss);
218 return new Mcr15(machInst, (IntRegIndex)miscReg, rt, iss);
219 } else {
190 case MISCREG_DCCMVAC:
191 return new FlushPipeInst(
192 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
193 case MISCREG_CP15ISB:
194 return new Isb(machInst, iss);
195 case MISCREG_CP15DSB:
196 return new Dsb(machInst, iss);
197 case MISCREG_CP15DMB:

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212 miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false;
213 }
214
215 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
216 if (isRead)
217 return new Mrc15(machInst, rt, (IntRegIndex)miscReg, iss);
218 return new Mcr15(machInst, (IntRegIndex)miscReg, rt, iss);
219 } else {
220 return new FailUnimplemented(csprintf("%s %s",
221 isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
222 machInst);
220 return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
221 csprintf("%s %s", isRead ? "mrc" : "mcr",
222 miscRegName[miscReg]));
223 }
224 }
225 }
226 '''
227}};
228
229def format McrMrc15() {{
230 decode_block = '''

--- 15 unchanged lines hidden (view full) ---

246 const MiscRegIndex miscReg = decodeCP15Reg64(crm, opc1);
247 const IntRegIndex rt = (IntRegIndex) (uint32_t) bits(machInst, 15, 12);
248 const IntRegIndex rt2 = (IntRegIndex) (uint32_t) bits(machInst, 19, 16);
249
250 const bool isRead = bits(machInst, 20);
251
252 switch (miscReg) {
253 case MISCREG_CP15_UNIMPL:
223 }
224 }
225 }
226 '''
227}};
228
229def format McrMrc15() {{
230 decode_block = '''

--- 15 unchanged lines hidden (view full) ---

246 const MiscRegIndex miscReg = decodeCP15Reg64(crm, opc1);
247 const IntRegIndex rt = (IntRegIndex) (uint32_t) bits(machInst, 15, 12);
248 const IntRegIndex rt2 = (IntRegIndex) (uint32_t) bits(machInst, 19, 16);
249
250 const bool isRead = bits(machInst, 20);
251
252 switch (miscReg) {
253 case MISCREG_CP15_UNIMPL:
254 return new FailUnimplemented(
254 return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
255 csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
255 csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
256 crm, opc1, isRead ? "read" : "write").c_str(),
257 machInst);
256 crm, opc1, isRead ? "read" : "write"));
258 default:
259 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
260 std::string full_mnem = csprintf("%s %s",
261 isRead ? "mrrc" : "mcrr", miscRegName[miscReg]);
262 warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
263
264 // Remove the warn flag and set the implemented flag. This
265 // prevents the instruction warning a second time, it also

--- 7 unchanged lines hidden (view full) ---

273
274 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
275 uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
276
277 if (isRead)
278 return new Mrrc15(machInst, (IntRegIndex) miscReg, rt2, rt, iss);
279 return new Mcrr15(machInst, rt2, rt, (IntRegIndex) miscReg, iss);
280 } else {
257 default:
258 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
259 std::string full_mnem = csprintf("%s %s",
260 isRead ? "mrrc" : "mcrr", miscRegName[miscReg]);
261 warn("\\tinstruction '%s' unimplemented\\n", full_mnem);
262
263 // Remove the warn flag and set the implemented flag. This
264 // prevents the instruction warning a second time, it also

--- 7 unchanged lines hidden (view full) ---

272
273 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
274 uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
275
276 if (isRead)
277 return new Mrrc15(machInst, (IntRegIndex) miscReg, rt2, rt, iss);
278 return new Mcrr15(machInst, rt2, rt, (IntRegIndex) miscReg, iss);
279 } else {
281 return new FailUnimplemented(csprintf("%s %s",
282 isRead ? "mrrc" : "mcrr", miscRegName[miscReg]).c_str(),
283 machInst);
280 return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst,
281 csprintf("%s %s",
282 isRead ? "mrrc" : "mcrr", miscRegName[miscReg]));
284 }
285 }
286 }
287 '''
288}};
289
290def format Mcrr15() {{
291 decode_block = '''
292 return decodeMcrrMrrc15(machInst);
293 '''
294}};
295
296def format Mrrc15() {{
297 decode_block = '''
298 return decodeMcrrMrrc15(machInst);
299 '''
300}};
283 }
284 }
285 }
286 '''
287}};
288
289def format Mcrr15() {{
290 decode_block = '''
291 return decodeMcrrMrrc15(machInst);
292 '''
293}};
294
295def format Mrrc15() {{
296 decode_block = '''
297 return decodeMcrrMrrc15(machInst);
298 '''
299}};