1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2012 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def format Svc() {{
41 decode_block = "return new Svc(machInst);"
42}};
43
44def format ArmMsrMrs() {{
45 decode_block = '''
46 {
47 const uint8_t byteMask = bits(machInst, 19, 16);
48 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
49 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
50 const uint32_t opcode = bits(machInst, 24, 21);
51 const bool useImm = bits(machInst, 25);
52
53 const uint32_t unrotated = bits(machInst, 7, 0);
54 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
55 const uint32_t imm = rotate_imm(unrotated, rotation);
56
57 switch (opcode) {
58 case 0x8:
59 return new MrsCpsr(machInst, rd);
60 case 0x9:
61 if (useImm) {
62 return new MsrCpsrImm(machInst, imm, byteMask);
63 } else {
64 return new MsrCpsrReg(machInst, rn, byteMask);
65 }
66 case 0xa:
67 return new MrsSpsr(machInst, rd);
68 case 0xb:
69 if (useImm) {
70 return new MsrSpsrImm(machInst, imm, byteMask);
71 } else {
72 return new MsrSpsrReg(machInst, rn, byteMask);
73 }
74 default:
75 return new Unknown(machInst);
76 }
77 }
78 '''
79}};
80
81let {{
82 header_output = '''
83 StaticInstPtr
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2012 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def format Svc() {{
41 decode_block = "return new Svc(machInst);"
42}};
43
44def format ArmMsrMrs() {{
45 decode_block = '''
46 {
47 const uint8_t byteMask = bits(machInst, 19, 16);
48 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
49 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
50 const uint32_t opcode = bits(machInst, 24, 21);
51 const bool useImm = bits(machInst, 25);
52
53 const uint32_t unrotated = bits(machInst, 7, 0);
54 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
55 const uint32_t imm = rotate_imm(unrotated, rotation);
56
57 switch (opcode) {
58 case 0x8:
59 return new MrsCpsr(machInst, rd);
60 case 0x9:
61 if (useImm) {
62 return new MsrCpsrImm(machInst, imm, byteMask);
63 } else {
64 return new MsrCpsrReg(machInst, rn, byteMask);
65 }
66 case 0xa:
67 return new MrsSpsr(machInst, rd);
68 case 0xb:
69 if (useImm) {
70 return new MsrSpsrImm(machInst, imm, byteMask);
71 } else {
72 return new MsrSpsrReg(machInst, rn, byteMask);
73 }
74 default:
75 return new Unknown(machInst);
76 }
77 }
78 '''
79}};
80
81let {{
82 header_output = '''
83 StaticInstPtr
|
85 '''
86 decoder_output = '''
87 StaticInstPtr
88 decodeMcrMrc14(ExtMachInst machInst)
89 {
90 const uint32_t opc1 = bits(machInst, 23, 21);
91 const uint32_t crn = bits(machInst, 19, 16);
92 const uint32_t opc2 = bits(machInst, 7, 5);
93 const uint32_t crm = bits(machInst, 3, 0);
94 const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
95 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
96
97 const bool isRead = bits(machInst, 20);
98
99 switch (miscReg) {
100 case MISCREG_NOP:
101 return new NopInst(machInst);
102 case NUM_MISCREGS:
103 return new FailUnimplemented(
104 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
105 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
106 machInst);
107 default:
108 if (isRead) {
109 return new Mrc14(machInst, rt, (IntRegIndex)miscReg);
110 } else {
111 return new Mcr14(machInst, (IntRegIndex)miscReg, rt);
112 }
113 }
114 }
115 '''
116}};
117
118def format McrMrc14() {{
119 decode_block = '''
120 return decodeMcrMrc14(machInst);
121 '''
122}};
123
124let {{
125 header_output = '''
126 StaticInstPtr
127 decodeMcrMrc15(ExtMachInst machInst);
128 '''
129 decoder_output = '''
130 StaticInstPtr
131 decodeMcrMrc15(ExtMachInst machInst)
132 {
133 const uint32_t opc1 = bits(machInst, 23, 21);
134 const uint32_t crn = bits(machInst, 19, 16);
135 const uint32_t opc2 = bits(machInst, 7, 5);
136 const uint32_t crm = bits(machInst, 3, 0);
137 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
138 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
139
140 const bool isRead = bits(machInst, 20);
141
142 switch (miscReg) {
143 case MISCREG_NOP:
144 return new NopInst(machInst);
145 case NUM_MISCREGS:
146 return new FailUnimplemented(
147 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
148 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
149 machInst);
150 case MISCREG_DCCISW:
151 return new WarnUnimplemented(
152 isRead ? "mrc dccisw" : "mcr dcisw", machInst);
153 case MISCREG_DCCIMVAC:
154 return new WarnUnimplemented(
155 isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
156 case MISCREG_DCIMVAC:
157 return new WarnUnimplemented(
158 isRead ? "mrc dcimvac" : "mcr dcimvac", machInst);
159 case MISCREG_DCCMVAC:
160 return new FlushPipeInst(
161 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
162 case MISCREG_DCCMVAU:
163 return new WarnUnimplemented(
164 isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
165 case MISCREG_CP15ISB:
166 return new Isb(machInst);
167 case MISCREG_CP15DSB:
168 return new Dsb(machInst);
169 case MISCREG_CP15DMB:
170 return new Dmb(machInst);
171 case MISCREG_ICIALLUIS:
172 return new WarnUnimplemented(
173 isRead ? "mrc icialluis" : "mcr icialluis", machInst);
174 case MISCREG_ICIMVAU:
175 return new WarnUnimplemented(
176 isRead ? "mrc icimvau" : "mcr icimvau", machInst);
177 case MISCREG_BPIMVA:
178 return new WarnUnimplemented(
179 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
180 case MISCREG_BPIALLIS:
181 return new WarnUnimplemented(
182 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
183 case MISCREG_BPIALL:
184 return new WarnUnimplemented(
185 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
186 case MISCREG_L2LATENCY:
187 return new WarnUnimplemented(
188 isRead ? "mrc l2latency" : "mcr l2latency", machInst);
189 case MISCREG_CRN15:
190 return new WarnUnimplemented(
191 isRead ? "mrc crn15" : "mcr crn15", machInst);
192
193 // Write only.
194 case MISCREG_TLBIALLIS:
195 case MISCREG_TLBIMVAIS:
196 case MISCREG_TLBIASIDIS:
197 case MISCREG_TLBIMVAAIS:
198 case MISCREG_ITLBIALL:
199 case MISCREG_ITLBIMVA:
200 case MISCREG_ITLBIASID:
201 case MISCREG_DTLBIALL:
202 case MISCREG_DTLBIMVA:
203 case MISCREG_DTLBIASID:
204 case MISCREG_TLBIALL:
205 case MISCREG_TLBIMVA:
206 case MISCREG_TLBIASID:
207 case MISCREG_TLBIMVAA:
208 if (isRead) {
209 return new Unknown(machInst);
210 } else {
211 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
212 }
213
214 // Read only in user mode.
215 case MISCREG_TPIDRURO:
216 if (isRead) {
217 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
218 } else {
219 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
220 }
221
222 // Read/write in user mode.
223 case MISCREG_TPIDRURW:
224 if (isRead) {
225 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
226 } else {
227 return new Mcr15User(machInst, (IntRegIndex)miscReg, rt);
228 }
229
230 // Read/write, priveleged only.
231 default:
232 if (miscReg >= MISCREG_CP15_UNIMP_START)
233 return new FailUnimplemented(csprintf("%s %s",
234 isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
235 machInst);
236 if (isRead) {
237 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
238 } else {
239 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
240 }
241 }
242 }
243 '''
244}};
245
246def format McrMrc15() {{
247 decode_block = '''
248 return decodeMcrMrc15(machInst);
249 '''
250}};
| 85 '''
86 decoder_output = '''
87 StaticInstPtr
88 decodeMcrMrc14(ExtMachInst machInst)
89 {
90 const uint32_t opc1 = bits(machInst, 23, 21);
91 const uint32_t crn = bits(machInst, 19, 16);
92 const uint32_t opc2 = bits(machInst, 7, 5);
93 const uint32_t crm = bits(machInst, 3, 0);
94 const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
95 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
96
97 const bool isRead = bits(machInst, 20);
98
99 switch (miscReg) {
100 case MISCREG_NOP:
101 return new NopInst(machInst);
102 case NUM_MISCREGS:
103 return new FailUnimplemented(
104 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
105 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
106 machInst);
107 default:
108 if (isRead) {
109 return new Mrc14(machInst, rt, (IntRegIndex)miscReg);
110 } else {
111 return new Mcr14(machInst, (IntRegIndex)miscReg, rt);
112 }
113 }
114 }
115 '''
116}};
117
118def format McrMrc14() {{
119 decode_block = '''
120 return decodeMcrMrc14(machInst);
121 '''
122}};
123
124let {{
125 header_output = '''
126 StaticInstPtr
127 decodeMcrMrc15(ExtMachInst machInst);
128 '''
129 decoder_output = '''
130 StaticInstPtr
131 decodeMcrMrc15(ExtMachInst machInst)
132 {
133 const uint32_t opc1 = bits(machInst, 23, 21);
134 const uint32_t crn = bits(machInst, 19, 16);
135 const uint32_t opc2 = bits(machInst, 7, 5);
136 const uint32_t crm = bits(machInst, 3, 0);
137 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
138 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
139
140 const bool isRead = bits(machInst, 20);
141
142 switch (miscReg) {
143 case MISCREG_NOP:
144 return new NopInst(machInst);
145 case NUM_MISCREGS:
146 return new FailUnimplemented(
147 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
148 crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
149 machInst);
150 case MISCREG_DCCISW:
151 return new WarnUnimplemented(
152 isRead ? "mrc dccisw" : "mcr dcisw", machInst);
153 case MISCREG_DCCIMVAC:
154 return new WarnUnimplemented(
155 isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
156 case MISCREG_DCIMVAC:
157 return new WarnUnimplemented(
158 isRead ? "mrc dcimvac" : "mcr dcimvac", machInst);
159 case MISCREG_DCCMVAC:
160 return new FlushPipeInst(
161 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
162 case MISCREG_DCCMVAU:
163 return new WarnUnimplemented(
164 isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
165 case MISCREG_CP15ISB:
166 return new Isb(machInst);
167 case MISCREG_CP15DSB:
168 return new Dsb(machInst);
169 case MISCREG_CP15DMB:
170 return new Dmb(machInst);
171 case MISCREG_ICIALLUIS:
172 return new WarnUnimplemented(
173 isRead ? "mrc icialluis" : "mcr icialluis", machInst);
174 case MISCREG_ICIMVAU:
175 return new WarnUnimplemented(
176 isRead ? "mrc icimvau" : "mcr icimvau", machInst);
177 case MISCREG_BPIMVA:
178 return new WarnUnimplemented(
179 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
180 case MISCREG_BPIALLIS:
181 return new WarnUnimplemented(
182 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
183 case MISCREG_BPIALL:
184 return new WarnUnimplemented(
185 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
186 case MISCREG_L2LATENCY:
187 return new WarnUnimplemented(
188 isRead ? "mrc l2latency" : "mcr l2latency", machInst);
189 case MISCREG_CRN15:
190 return new WarnUnimplemented(
191 isRead ? "mrc crn15" : "mcr crn15", machInst);
192
193 // Write only.
194 case MISCREG_TLBIALLIS:
195 case MISCREG_TLBIMVAIS:
196 case MISCREG_TLBIASIDIS:
197 case MISCREG_TLBIMVAAIS:
198 case MISCREG_ITLBIALL:
199 case MISCREG_ITLBIMVA:
200 case MISCREG_ITLBIASID:
201 case MISCREG_DTLBIALL:
202 case MISCREG_DTLBIMVA:
203 case MISCREG_DTLBIASID:
204 case MISCREG_TLBIALL:
205 case MISCREG_TLBIMVA:
206 case MISCREG_TLBIASID:
207 case MISCREG_TLBIMVAA:
208 if (isRead) {
209 return new Unknown(machInst);
210 } else {
211 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
212 }
213
214 // Read only in user mode.
215 case MISCREG_TPIDRURO:
216 if (isRead) {
217 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
218 } else {
219 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
220 }
221
222 // Read/write in user mode.
223 case MISCREG_TPIDRURW:
224 if (isRead) {
225 return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
226 } else {
227 return new Mcr15User(machInst, (IntRegIndex)miscReg, rt);
228 }
229
230 // Read/write, priveleged only.
231 default:
232 if (miscReg >= MISCREG_CP15_UNIMP_START)
233 return new FailUnimplemented(csprintf("%s %s",
234 isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
235 machInst);
236 if (isRead) {
237 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
238 } else {
239 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
240 }
241 }
242 }
243 '''
244}};
245
246def format McrMrc15() {{
247 decode_block = '''
248 return decodeMcrMrc15(machInst);
249 '''
250}};
|