1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def format Svc() {{ 41 decode_block = "return new Svc(machInst);" 42}}; 43 44def format ArmMsrMrs() {{ 45 decode_block = ''' 46 { 47 const uint8_t byteMask = bits(machInst, 19, 16); 48 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 49 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 50 const uint32_t opcode = bits(machInst, 24, 21); 51 const bool useImm = bits(machInst, 25); 52 53 const uint32_t unrotated = bits(machInst, 7, 0); 54 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 55 const uint32_t imm = rotate_imm(unrotated, rotation); 56 57 switch (opcode) { 58 case 0x8: 59 return new MrsCpsr(machInst, rd); 60 case 0x9: 61 if (useImm) { 62 return new MsrCpsrImm(machInst, imm, byteMask); 63 } else { 64 return new MsrCpsrReg(machInst, rn, byteMask); 65 } 66 case 0xa: 67 return new MrsSpsr(machInst, rd); 68 case 0xb: 69 if (useImm) { 70 return new MsrSpsrImm(machInst, imm, byteMask); 71 } else { 72 return new MsrSpsrReg(machInst, rn, byteMask); 73 } 74 default: 75 return new Unknown(machInst); 76 } 77 } 78 ''' 79}}; 80
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def format Svc() {{ 41 decode_block = "return new Svc(machInst);" 42}}; 43 44def format ArmMsrMrs() {{ 45 decode_block = ''' 46 { 47 const uint8_t byteMask = bits(machInst, 19, 16); 48 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 49 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 50 const uint32_t opcode = bits(machInst, 24, 21); 51 const bool useImm = bits(machInst, 25); 52 53 const uint32_t unrotated = bits(machInst, 7, 0); 54 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 55 const uint32_t imm = rotate_imm(unrotated, rotation); 56 57 switch (opcode) { 58 case 0x8: 59 return new MrsCpsr(machInst, rd); 60 case 0x9: 61 if (useImm) { 62 return new MsrCpsrImm(machInst, imm, byteMask); 63 } else { 64 return new MsrCpsrReg(machInst, rn, byteMask); 65 } 66 case 0xa: 67 return new MrsSpsr(machInst, rd); 68 case 0xb: 69 if (useImm) { 70 return new MsrSpsrImm(machInst, imm, byteMask); 71 } else { 72 return new MsrSpsrReg(machInst, rn, byteMask); 73 } 74 default: 75 return new Unknown(machInst); 76 } 77 } 78 ''' 79}}; 80
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81def format McrMrc15() {{ 82 decode_block = '''
| 81let {{ 82 header_output = ''' 83 StaticInstPtr 84 decodeMcrMrc15(ExtMachInst machInst); 85 ''' 86 decoder_output = ''' 87 StaticInstPtr 88 decodeMcrMrc15(ExtMachInst machInst)
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83 { 84 const uint32_t opc1 = bits(machInst, 23, 21); 85 const uint32_t crn = bits(machInst, 19, 16); 86 const uint32_t opc2 = bits(machInst, 7, 5); 87 const uint32_t crm = bits(machInst, 3, 0); 88 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2); 89 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 90 91 const bool isRead = bits(machInst, 20); 92 93 switch (miscReg) { 94 case MISCREG_NOP: 95 return new NopInst(machInst); 96 case NUM_MISCREGS: 97 return new Unknown(machInst); 98 case MISCREG_DCCISW: 99 return new WarnUnimplemented( 100 isRead ? "mrc dccisw" : "mcr dcisw", machInst); 101 case MISCREG_DCCIMVAC: 102 return new WarnUnimplemented( 103 isRead ? "mrc dccimvac" : "mcr dccimvac", machInst); 104 case MISCREG_DCCMVAC: 105 return new WarnUnimplemented( 106 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst); 107 case MISCREG_CP15ISB: 108 return new WarnUnimplemented( 109 isRead ? "mrc cp15isb" : "mcr cp15isb", machInst); 110 case MISCREG_CP15DSB: 111 return new WarnUnimplemented( 112 isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst); 113 case MISCREG_CP15DMB: 114 return new WarnUnimplemented( 115 isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst); 116 case MISCREG_ICIALLUIS: 117 return new WarnUnimplemented( 118 isRead ? "mrc icialluis" : "mcr icialluis", machInst); 119 case MISCREG_ICIMVAU: 120 return new WarnUnimplemented( 121 isRead ? "mrc icimvau" : "mcr icimvau", machInst); 122 case MISCREG_BPIMVA: 123 return new WarnUnimplemented( 124 isRead ? "mrc bpimva" : "mcr bpimva", machInst); 125 case MISCREG_BPIALLIS: 126 return new WarnUnimplemented( 127 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst); 128 case MISCREG_BPIALL: 129 return new WarnUnimplemented( 130 isRead ? "mrc bpiall" : "mcr bpiall", machInst); 131 case MISCREG_TLBIALLIS: 132 return new WarnUnimplemented( 133 isRead ? "mrc tlbiallis" : "mcr tlbiallis", machInst); 134 case MISCREG_TLBIMVAIS: 135 return new WarnUnimplemented( 136 isRead ? "mrc tlbimvais" : "mcr tlbimvais", machInst); 137 case MISCREG_TLBIASIDIS: 138 return new WarnUnimplemented( 139 isRead ? "mrc tlbiasidis" : "mcr tlbiasidis", machInst); 140 case MISCREG_TLBIMVAAIS: 141 return new WarnUnimplemented( 142 isRead ? "mrc tlbimvaais" : "mcr tlbimvaais", machInst); 143 case MISCREG_ITLBIALL: 144 return new WarnUnimplemented( 145 isRead ? "mrc itlbiall" : "mcr itlbiall", machInst); 146 case MISCREG_ITLBIMVA: 147 return new WarnUnimplemented( 148 isRead ? "mrc itlbimva" : "mcr itlbimva", machInst); 149 case MISCREG_ITLBIASID: 150 return new WarnUnimplemented( 151 isRead ? "mrc itlbiasid" : "mcr itlbiasid", machInst); 152 case MISCREG_DTLBIALL: 153 return new WarnUnimplemented( 154 isRead ? "mrc dtlbiall" : "mcr dtlbiall", machInst); 155 case MISCREG_DTLBIMVA: 156 return new WarnUnimplemented( 157 isRead ? "mrc dtlbimva" : "mcr dtlbimva", machInst); 158 case MISCREG_DTLBIASID: 159 return new WarnUnimplemented( 160 isRead ? "mrc dtlbiasid" : "mcr dtlbiasid", machInst); 161 case MISCREG_TLBIALL: 162 return new WarnUnimplemented( 163 isRead ? "mrc tlbiall" : "mcr tlbiall", machInst); 164 case MISCREG_TLBIMVA: 165 return new WarnUnimplemented( 166 isRead ? "mrc tlbimva" : "mcr tlbimva", machInst); 167 case MISCREG_TLBIASID: 168 return new WarnUnimplemented( 169 isRead ? "mrc tlbiasid" : "mcr tlbiasid", machInst); 170 case MISCREG_TLBIMVAA: 171 return new WarnUnimplemented( 172 isRead ? "mrc tlbimvaa" : "mcr tlbimvaa", machInst); 173 default: 174 if (isRead) { 175 return new Mrc15(machInst, rt, (IntRegIndex)miscReg); 176 } else { 177 return new Mcr15(machInst, (IntRegIndex)miscReg, rt); 178 } 179 } 180 } 181 ''' 182}};
| 89 { 90 const uint32_t opc1 = bits(machInst, 23, 21); 91 const uint32_t crn = bits(machInst, 19, 16); 92 const uint32_t opc2 = bits(machInst, 7, 5); 93 const uint32_t crm = bits(machInst, 3, 0); 94 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2); 95 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 96 97 const bool isRead = bits(machInst, 20); 98 99 switch (miscReg) { 100 case MISCREG_NOP: 101 return new NopInst(machInst); 102 case NUM_MISCREGS: 103 return new Unknown(machInst); 104 case MISCREG_DCCISW: 105 return new WarnUnimplemented( 106 isRead ? "mrc dccisw" : "mcr dcisw", machInst); 107 case MISCREG_DCCIMVAC: 108 return new WarnUnimplemented( 109 isRead ? "mrc dccimvac" : "mcr dccimvac", machInst); 110 case MISCREG_DCCMVAC: 111 return new WarnUnimplemented( 112 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst); 113 case MISCREG_CP15ISB: 114 return new WarnUnimplemented( 115 isRead ? "mrc cp15isb" : "mcr cp15isb", machInst); 116 case MISCREG_CP15DSB: 117 return new WarnUnimplemented( 118 isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst); 119 case MISCREG_CP15DMB: 120 return new WarnUnimplemented( 121 isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst); 122 case MISCREG_ICIALLUIS: 123 return new WarnUnimplemented( 124 isRead ? "mrc icialluis" : "mcr icialluis", machInst); 125 case MISCREG_ICIMVAU: 126 return new WarnUnimplemented( 127 isRead ? "mrc icimvau" : "mcr icimvau", machInst); 128 case MISCREG_BPIMVA: 129 return new WarnUnimplemented( 130 isRead ? "mrc bpimva" : "mcr bpimva", machInst); 131 case MISCREG_BPIALLIS: 132 return new WarnUnimplemented( 133 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst); 134 case MISCREG_BPIALL: 135 return new WarnUnimplemented( 136 isRead ? "mrc bpiall" : "mcr bpiall", machInst); 137 case MISCREG_TLBIALLIS: 138 return new WarnUnimplemented( 139 isRead ? "mrc tlbiallis" : "mcr tlbiallis", machInst); 140 case MISCREG_TLBIMVAIS: 141 return new WarnUnimplemented( 142 isRead ? "mrc tlbimvais" : "mcr tlbimvais", machInst); 143 case MISCREG_TLBIASIDIS: 144 return new WarnUnimplemented( 145 isRead ? "mrc tlbiasidis" : "mcr tlbiasidis", machInst); 146 case MISCREG_TLBIMVAAIS: 147 return new WarnUnimplemented( 148 isRead ? "mrc tlbimvaais" : "mcr tlbimvaais", machInst); 149 case MISCREG_ITLBIALL: 150 return new WarnUnimplemented( 151 isRead ? "mrc itlbiall" : "mcr itlbiall", machInst); 152 case MISCREG_ITLBIMVA: 153 return new WarnUnimplemented( 154 isRead ? "mrc itlbimva" : "mcr itlbimva", machInst); 155 case MISCREG_ITLBIASID: 156 return new WarnUnimplemented( 157 isRead ? "mrc itlbiasid" : "mcr itlbiasid", machInst); 158 case MISCREG_DTLBIALL: 159 return new WarnUnimplemented( 160 isRead ? "mrc dtlbiall" : "mcr dtlbiall", machInst); 161 case MISCREG_DTLBIMVA: 162 return new WarnUnimplemented( 163 isRead ? "mrc dtlbimva" : "mcr dtlbimva", machInst); 164 case MISCREG_DTLBIASID: 165 return new WarnUnimplemented( 166 isRead ? "mrc dtlbiasid" : "mcr dtlbiasid", machInst); 167 case MISCREG_TLBIALL: 168 return new WarnUnimplemented( 169 isRead ? "mrc tlbiall" : "mcr tlbiall", machInst); 170 case MISCREG_TLBIMVA: 171 return new WarnUnimplemented( 172 isRead ? "mrc tlbimva" : "mcr tlbimva", machInst); 173 case MISCREG_TLBIASID: 174 return new WarnUnimplemented( 175 isRead ? "mrc tlbiasid" : "mcr tlbiasid", machInst); 176 case MISCREG_TLBIMVAA: 177 return new WarnUnimplemented( 178 isRead ? "mrc tlbimvaa" : "mcr tlbimvaa", machInst); 179 default: 180 if (isRead) { 181 return new Mrc15(machInst, rt, (IntRegIndex)miscReg); 182 } else { 183 return new Mcr15(machInst, (IntRegIndex)miscReg, rt); 184 } 185 } 186 } 187 ''' 188}};
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| 189 190def format McrMrc15() {{ 191 decode_block = ''' 192 return decodeMcrMrc15(machInst); 193 ''' 194}};
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