1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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133 isRead ? "mrc bpimva" : "mcr bpimva", machInst);
134 case MISCREG_BPIALLIS:
135 return new WarnUnimplemented(
136 isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
137 case MISCREG_BPIALL:
138 return new WarnUnimplemented(
139 isRead ? "mrc bpiall" : "mcr bpiall", machInst);
140 case MISCREG_TLBIALLIS:
141 case MISCREG_TLBIMVAIS:
142 case MISCREG_TLBIASIDIS:
143 case MISCREG_TLBIMVAAIS:
144 case MISCREG_ITLBIALL:
145 case MISCREG_ITLBIMVA:
146 case MISCREG_ITLBIASID:
147 case MISCREG_DTLBIALL:
148 case MISCREG_DTLBIMVA:
149 case MISCREG_DTLBIASID:
150 case MISCREG_TLBIALL:
151 case MISCREG_TLBIMVA:
152 case MISCREG_TLBIASID:
153 case MISCREG_TLBIMVAA:
154 if (isRead) {
155 return new Unknown(machInst);
156 } else {
157 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
158 }
159
160 default:
161 if (isRead) {
162 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
163 } else {
164 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
165 }
166 }
167 }
168 '''
169}};
170
171def format McrMrc15() {{
172 decode_block = '''
173 return decodeMcrMrc15(machInst);
174 '''
175}};