mem.isa (7309:35b6ca04e5b9) mem.isa (7314:f254f66afb11)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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258 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2),
259 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False)
260 }
261}};
262
263def format Thumb32SrsRfe() {{
264 decode_block = '''
265 {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 249 unchanged lines hidden (view full) ---

258 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2),
259 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False)
260 }
261}};
262
263def format Thumb32SrsRfe() {{
264 decode_block = '''
265 {
266 const bool wb = (bits(machInst, 21) == 1);
267 const bool add = (bits(machInst, 24, 23) == 0x3);
266 if (bits(machInst, 20) == 1) {
268 if (bits(machInst, 20) == 1) {
267 const bool add = (bits(machInst, 24, 23) == 0x3);
268 // post == add
269 // post == add
269 const bool wb = (bits(machInst, 21) == 1);
270 const IntRegIndex rn =
271 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
272 if (!add && !wb) {
273 return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb);
274 } else if (add && !wb) {
275 return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb);
276 } else if (!add && wb) {
277 return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb);
278 } else {
279 return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb);
280 }
281 } else {
270 const IntRegIndex rn =
271 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
272 if (!add && !wb) {
273 return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb);
274 } else if (add && !wb) {
275 return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb);
276 } else if (!add && wb) {
277 return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb);
278 } else {
279 return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb);
280 }
281 } else {
282 return new WarnUnimplemented("srs", machInst);
282 const uint32_t mode = bits(machInst, 4, 0);
283 if (!add && !wb) {
284 return new %(srs)s(machInst, mode,
285 SrsOp::DecrementBefore, wb);
286 } else if (add && !wb) {
287 return new %(srs_u)s(machInst, mode,
288 SrsOp::IncrementAfter, wb);
289 } else if (!add && wb) {
290 return new %(srs_w)s(machInst, mode,
291 SrsOp::DecrementBefore, wb);
292 } else {
293 return new %(srs_uw)s(machInst, mode,
294 SrsOp::IncrementAfter, wb);
295 }
283 }
284 }
285 ''' % {
286 "rfe" : "RFE_" + loadImmClassName(False, False, False, 8),
287 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
288 "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8),
296 }
297 }
298 ''' % {
299 "rfe" : "RFE_" + loadImmClassName(False, False, False, 8),
300 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
301 "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8),
289 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8)
302 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
303 "srs" : "SRS_" + storeImmClassName(False, False, False, 8),
304 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
305 "srs_w" : "SRS_" + storeImmClassName(False, False, True, 8),
306 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8)
290 }
291}};
292
293def format Thumb32LdrStrDExTbh() {{
294 decode_block = '''
295 {
296 const uint32_t op1 = bits(machInst, 24, 23);
297 const uint32_t op2 = bits(machInst, 21, 20);

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308}};
309
310def format Thumb32LdrStrDExTbh() {{
311 decode_block = '''
312 {
313 const uint32_t op1 = bits(machInst, 24, 23);
314 const uint32_t op2 = bits(machInst, 21, 20);

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