mem.isa (7293:a907ebdb7ee9) mem.isa (7304:ce1844ce6412)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 215 unchanged lines hidden (view full) ---

224 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
225 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
226 switch (PUBWL) {
227 case 0x10:
228 return new Swp(machInst, rt, rt2, rn);
229 case 0x14:
230 return new Swpb(machInst, rt, rt2, rn);
231 case 0x18:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 215 unchanged lines hidden (view full) ---

224 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
225 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
226 switch (PUBWL) {
227 case 0x10:
228 return new Swp(machInst, rt, rt2, rn);
229 case 0x14:
230 return new Swpb(machInst, rt, rt2, rn);
231 case 0x18:
232 return new WarnUnimplemented("strex", machInst);
232 return new %(strex)s(machInst, rt, rt2, rn, true, 0);
233 case 0x19:
234 return new %(ldrex)s(machInst, rt, rn, true, 0);
235 case 0x1a:
233 case 0x19:
234 return new %(ldrex)s(machInst, rt, rn, true, 0);
235 case 0x1a:
236 return new WarnUnimplemented("strexd", machInst);
236 return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0);
237 case 0x1b:
238 return new WarnUnimplemented("ldrexd", machInst);
239 case 0x1c:
237 case 0x1b:
238 return new WarnUnimplemented("ldrexd", machInst);
239 case 0x1c:
240 return new WarnUnimplemented("strexb", machInst);
240 return new %(strexb)s(machInst, rt, rt2, rn, true, 0);
241 case 0x1d:
242 return new %(ldrexb)s(machInst, rt, rn, true, 0);
243 case 0x1e:
241 case 0x1d:
242 return new %(ldrexb)s(machInst, rt, rn, true, 0);
243 case 0x1e:
244 return new WarnUnimplemented("strexh", machInst);
244 return new %(strexh)s(machInst, rt, rt2, rn, true, 0);
245 case 0x1f:
246 return new %(ldrexh)s(machInst, rt, rn, true, 0);
247 default:
248 return new Unknown(machInst);
249 }
250 }
251 ''' % {
252 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
253 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
245 case 0x1f:
246 return new %(ldrexh)s(machInst, rt, rn, true, 0);
247 default:
248 return new Unknown(machInst);
249 }
250 }
251 ''' % {
252 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
253 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
254 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2)
254 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2),
255 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4),
256 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1),
257 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2),
258 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False)
255 }
256}};
257
258def format Thumb32SrsRfe() {{
259 decode_block = '''
260 {
261 if (bits(machInst, 20) == 1) {
262 const bool add = (bits(machInst, 24, 23) == 0x3);

--- 26 unchanged lines hidden (view full) ---

289 decode_block = '''
290 {
291 const uint32_t op1 = bits(machInst, 24, 23);
292 const uint32_t op2 = bits(machInst, 21, 20);
293 const uint32_t op3 = bits(machInst, 7, 4);
294 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
295 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
296 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
259 }
260}};
261
262def format Thumb32SrsRfe() {{
263 decode_block = '''
264 {
265 if (bits(machInst, 20) == 1) {
266 const bool add = (bits(machInst, 24, 23) == 0x3);

--- 26 unchanged lines hidden (view full) ---

293 decode_block = '''
294 {
295 const uint32_t op1 = bits(machInst, 24, 23);
296 const uint32_t op2 = bits(machInst, 21, 20);
297 const uint32_t op3 = bits(machInst, 7, 4);
298 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
299 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
300 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
301 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
297 const uint32_t imm8 = bits(machInst, 7, 0);
298 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
299 if (op1 == 0) {
300 const uint32_t imm = bits(machInst, 7, 0) << 2;
301 if (op2 == 0) {
302 const uint32_t imm8 = bits(machInst, 7, 0);
303 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
304 if (op1 == 0) {
305 const uint32_t imm = bits(machInst, 7, 0) << 2;
306 if (op2 == 0) {
302 return new WarnUnimplemented("strex", machInst);
307 return new %(strex)s(machInst, rt2, rt, rn, true, imm);
303 } else {
304 return new %(ldrex)s(machInst, rt, rn, true, imm);
305 }
306 } else {
307 if (op2 == 0) {
308 switch (op3) {
309 case 0x4:
308 } else {
309 return new %(ldrex)s(machInst, rt, rn, true, imm);
310 }
311 } else {
312 if (op2 == 0) {
313 switch (op3) {
314 case 0x4:
310 return new WarnUnimplemented("strexb", machInst);
315 return new %(strexb)s(machInst, rd, rt, rn, true, 0);
311 case 0x5:
316 case 0x5:
312 return new WarnUnimplemented("strexh", machInst);
317 return new %(strexh)s(machInst, rd, rt, rn, true, 0);
313 case 0x7:
318 case 0x7:
314 return new WarnUnimplemented("strexd", machInst);
319 return new %(strexd)s(machInst, rd, rt,
320 rt2, rn, true, 0);
315 default:
316 return new Unknown(machInst);
317 }
318 } else {
319 switch (op3) {
320 case 0x0:
321 return new WarnUnimplemented("tbb", machInst);
322 case 0x1:

--- 50 unchanged lines hidden (view full) ---

373 }
374 }
375 }
376 ''' % {
377 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
378 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
379 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2),
380 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False),
321 default:
322 return new Unknown(machInst);
323 }
324 } else {
325 switch (op3) {
326 case 0x0:
327 return new WarnUnimplemented("tbb", machInst);
328 case 0x1:

--- 50 unchanged lines hidden (view full) ---

379 }
380 }
381 }
382 ''' % {
383 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
384 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
385 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2),
386 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False),
387 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4),
388 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1),
389 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2),
390 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False),
381 "ldrd_w" : loadDoubleImmClassName(True, False, True),
382 "ldrd_uw" : loadDoubleImmClassName(True, True, True),
383 "ldrd_p" : loadDoubleImmClassName(False, False, False),
384 "ldrd_pw" : loadDoubleImmClassName(False, False, True),
385 "ldrd_pu" : loadDoubleImmClassName(False, True, False),
386 "ldrd_puw" : loadDoubleImmClassName(False, True, True),
387 "strd_w" : storeDoubleImmClassName(True, False, True),
388 "strd_uw" : storeDoubleImmClassName(True, True, True),

--- 638 unchanged lines hidden --- 		391 "ldrd_w" : loadDoubleImmClassName(True, False, True),
392 "ldrd_uw" : loadDoubleImmClassName(True, True, True),
393 "ldrd_p" : loadDoubleImmClassName(False, False, False),
394 "ldrd_pw" : loadDoubleImmClassName(False, False, True),
395 "ldrd_pu" : loadDoubleImmClassName(False, True, False),
396 "ldrd_puw" : loadDoubleImmClassName(False, True, True),
397 "strd_w" : storeDoubleImmClassName(True, False, True),
398 "strd_uw" : storeDoubleImmClassName(True, True, True),

--- 638 unchanged lines hidden ---