mem.isa (7280:fe6d787ed4c9) mem.isa (7290:ea9189fbb84f)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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464 "imm_puw" : storeImmClassName(False, True, True, size=size)
465 }
466 decode = '''
467 {
468 uint32_t op1 = bits(machInst, 23, 21);
469 uint32_t op2 = bits(machInst, 11, 6);
470 bool op2Puw = ((op2 & 0x24) == 0x24 ||
471 (op2 & 0x3c) == 0x30);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 455 unchanged lines hidden (view full) ---

464 "imm_puw" : storeImmClassName(False, True, True, size=size)
465 }
466 decode = '''
467 {
468 uint32_t op1 = bits(machInst, 23, 21);
469 uint32_t op2 = bits(machInst, 11, 6);
470 bool op2Puw = ((op2 & 0x24) == 0x24 ||
471 (op2 & 0x3c) == 0x30);
472 if (RN == 0xf) {
473 return new Unknown(machInst);
474 }
472 if (op1 == 4) {
473 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0);
474 } else if (op1 == 0 && op2Puw) {
475 %(strb_puw)s;
476 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) {
477 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0);
478 } else if (op1 == 0 && op2 == 0) {
479 return new %(strb_reg)s(machInst, RT, RN, true,

--- 514 unchanged lines hidden --- 		475 if (op1 == 4) {
476 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0);
477 } else if (op1 == 0 && op2Puw) {
478 %(strb_puw)s;
479 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) {
480 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0);
481 } else if (op1 == 0 && op2 == 0) {
482 return new %(strb_reg)s(machInst, RT, RN, true,

--- 514 unchanged lines hidden ---