mem.isa (7279:157b02cc0ba1) mem.isa (7280:fe6d787ed4c9)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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258def format Thumb32LdrStrDExTbh() {{
259 decode_block = '''
260 {
261 const uint32_t op1 = bits(machInst, 24, 23);
262 const uint32_t op2 = bits(machInst, 21, 20);
263 const uint32_t op3 = bits(machInst, 7, 4);
264 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
265 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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258def format Thumb32LdrStrDExTbh() {{
259 decode_block = '''
260 {
261 const uint32_t op1 = bits(machInst, 24, 23);
262 const uint32_t op2 = bits(machInst, 21, 20);
263 const uint32_t op3 = bits(machInst, 7, 4);
264 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
265 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
266 /* This isn't used yet, and that makes gcc upset. */
267 //const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
266 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
267 const uint32_t imm8 = bits(machInst, 7, 0);
268 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
269 if (op1 == 0) {
270 const uint32_t imm = bits(machInst, 7, 0) << 2;
271 if (op2 == 0) {
272 return new WarnUnimplemented("strex", machInst);
273 } else {
274 return new %(ldrex)s(machInst, rt, rn, true, imm);
275 }

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291 return new WarnUnimplemented("tbb", machInst);
292 case 0x1:
293 return new WarnUnimplemented("tbh", machInst);
294 case 0x4:
295 return new %(ldrexb)s(machInst, rt, rn, true, 0);
296 case 0x5:
297 return new %(ldrexh)s(machInst, rt, rn, true, 0);
298 case 0x7:
268 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
269 if (op1 == 0) {
270 const uint32_t imm = bits(machInst, 7, 0) << 2;
271 if (op2 == 0) {
272 return new WarnUnimplemented("strex", machInst);
273 } else {
274 return new %(ldrex)s(machInst, rt, rn, true, imm);
275 }

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291 return new WarnUnimplemented("tbb", machInst);
292 case 0x1:
293 return new WarnUnimplemented("tbh", machInst);
294 case 0x4:
295 return new %(ldrexb)s(machInst, rt, rn, true, 0);
296 case 0x5:
297 return new %(ldrexh)s(machInst, rt, rn, true, 0);
298 case 0x7:
299 return new WarnUnimplemented("ldrexd", machInst);
299 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0);
300 default:
301 return new Unknown(machInst);
302 }
303 }
304 }
305 } else {
300 default:
301 return new Unknown(machInst);
302 }
303 }
304 }
305 } else {
306 const uint32_t puw = (bits(machInst, 24, 23) << 1) |
307 bits(machInst, 21);
308 const uint32_t dimm = imm8 << 2;
306 if (bits(op2, 0) == 0) {
309 if (bits(op2, 0) == 0) {
307 return new WarnUnimplemented("strd", machInst);
310 switch (puw) {
311 case 0x1:
312 return new %(strd_w)s(machInst, rt, rt2, rn, false, dimm);
313 case 0x3:
314 return new %(strd_uw)s(machInst, rt, rt2, rn, true, dimm);
315 case 0x4:
316 return new %(strd_p)s(machInst, rt, rt2, rn, false, dimm);
317 case 0x5:
318 return new %(strd_pw)s(machInst, rt, rt2, rn, false, dimm);
319 case 0x6:
320 return new %(strd_pu)s(machInst, rt, rt2, rn, true, dimm);
321 case 0x7:
322 return new %(strd_puw)s(machInst, rt, rt2, rn, true, dimm);
323 default:
324 return new Unknown(machInst);
325 }
308 } else {
326 } else {
309 return new WarnUnimplemented("ldrd", machInst);
327 switch (puw) {
328 case 0x1:
329 return new %(ldrd_w)s(machInst, rt, rt2, rn, false, dimm);
330 case 0x3:
331 return new %(ldrd_uw)s(machInst, rt, rt2, rn, true, dimm);
332 case 0x4:
333 return new %(ldrd_p)s(machInst, rt, rt2, rn, false, dimm);
334 case 0x5:
335 return new %(ldrd_pw)s(machInst, rt, rt2, rn, false, dimm);
336 case 0x6:
337 return new %(ldrd_pu)s(machInst, rt, rt2, rn, true, dimm);
338 case 0x7:
339 return new %(ldrd_puw)s(machInst, rt, rt2, rn, true, dimm);
340 default:
341 return new Unknown(machInst);
342 }
310 }
311 }
312 }
313 ''' % {
314 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
315 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
343 }
344 }
345 }
346 ''' % {
347 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
348 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
316 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2)
349 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2),
350 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False),
351 "ldrd_w" : loadDoubleImmClassName(True, False, True),
352 "ldrd_uw" : loadDoubleImmClassName(True, True, True),
353 "ldrd_p" : loadDoubleImmClassName(False, False, False),
354 "ldrd_pw" : loadDoubleImmClassName(False, False, True),
355 "ldrd_pu" : loadDoubleImmClassName(False, True, False),
356 "ldrd_puw" : loadDoubleImmClassName(False, True, True),
357 "strd_w" : storeDoubleImmClassName(True, False, True),
358 "strd_uw" : storeDoubleImmClassName(True, True, True),
359 "strd_p" : storeDoubleImmClassName(False, False, False),
360 "strd_pw" : storeDoubleImmClassName(False, False, True),
361 "strd_pu" : storeDoubleImmClassName(False, True, False),
362 "strd_puw" : storeDoubleImmClassName(False, True, True)
317 }
318}};
319
320def format Thumb32LoadWord() {{
321 decode = '''
322 {
323 uint32_t op1 = bits(machInst, 24, 23);
324 if (bits(op1, 1) == 0) {

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364}};
365
366def format Thumb32LoadWord() {{
367 decode = '''
368 {
369 uint32_t op1 = bits(machInst, 24, 23);
370 if (bits(op1, 1) == 0) {

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