mem.isa (7277:85e4f11ad2c3) mem.isa (7278:562ced200e54)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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463 "str_imm" : storeImmClassName(False, True, False),
464 "str_puw" : buildPuwDecode(4),
465 "strt" : storeImmClassName(False, True, False, user=True),
466 "str_reg" : storeRegClassName(False, True, False)
467 }
468 decode_block = decode % classNames
469}};
470
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 454 unchanged lines hidden (view full) ---

463 "str_imm" : storeImmClassName(False, True, False),
464 "str_puw" : buildPuwDecode(4),
465 "strt" : storeImmClassName(False, True, False, user=True),
466 "str_reg" : storeRegClassName(False, True, False)
467 }
468 decode_block = decode % classNames
469}};
470
471def format LoadByteMemoryHints() {{
472 decode = '''
473 {
474 const uint32_t op1 = bits(machInst, 24, 23);
475 const uint32_t op2 = bits(machInst, 11, 6);
476 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
477 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
478 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
479 const uint32_t imm12 = bits(machInst, 11, 0);
480 const uint32_t imm8 = bits(machInst, 7, 0);
481 bool pldw = bits(machInst, 21);
482 const uint32_t imm2 = bits(machInst, 5, 4);
483 if (rn == 0xf) {
484 if (rt == 0xf) {
485 const bool add = bits(machInst, 23);
486 if (bits(op1, 1) == 1) {
487 if (add) {
488 return new %(pli_iulit)s(machInst, INTREG_ZERO,
489 INTREG_PC, true, imm12);
490 } else {
491 return new %(pli_ilit)s(machInst, INTREG_ZERO,
492 INTREG_PC, false, imm12);
493 }
494 } else {
495 if (add) {
496 return new %(pld_iulit)s(machInst, INTREG_ZERO,
497 INTREG_PC, true, imm12);
498 } else {
499 return new %(pld_ilit)s(machInst, INTREG_ZERO,
500 INTREG_PC, false, imm12);
501 }
502 }
503 } else {
504 if (bits(op1, 1) == 1) {
505 if (bits(machInst, 23)) {
506 return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC,
507 true, imm12);
508 } else {
509 return new %(ldrsb_lit)s(machInst, rt, INTREG_PC,
510 false, imm12);
511 }
512 } else {
513 if (bits(machInst, 23)) {
514 return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC,
515 true, imm12);
516 } else {
517 return new %(ldrb_lit)s(machInst, rt, INTREG_PC,
518 false, imm12);
519 }
520 }
521 }
522 } else if (rt == 0xf) {
523 switch (op1) {
524 case 0x0:
525 if (op2 == 0x0) {
526 if (pldw) {
527 return new %(pldw_radd)s(machInst, INTREG_ZERO,
528 rn, true, imm2, LSL, rm);
529 } else {
530 return new %(pld_radd)s(machInst, INTREG_ZERO,
531 rn, true, imm2, LSL, rm);
532 }
533 } else if (bits(op2, 5, 2) == 0xc) {
534 if (pldw) {
535 return new %(pldw_isub)s(machInst, INTREG_ZERO,
536 rn, false, imm8);
537 } else {
538 return new %(pld_isub)s(machInst, INTREG_ZERO,
539 rn, false, imm8);
540 }
541 }
542 break;
543 case 0x1:
544 if (pldw) {
545 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
546 rn, true, imm12);
547 } else {
548 return new %(pld_iadd)s(machInst, INTREG_ZERO,
549 rn, true, imm12);
550 }
551 case 0x2:
552 if (op2 == 0x0) {
553 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
554 true, imm2, LSL, rm);
555 } else if (bits(op2, 5, 2) == 0xc) {
556 return new %(pli_ilit)s(machInst, INTREG_ZERO,
557 INTREG_PC, false, imm8);
558 }
559 break;
560 case 0x3:
561 return new %(pli_iulit)s(machInst, INTREG_ZERO,
562 INTREG_PC, true, imm12);
563 }
564 return new Unknown(machInst);
565 } else {
566 switch (op1) {
567 case 0x0:
568 if (op2 == 0) {
569 return new %(ldrb_radd)s(machInst, rt, rn, true,
570 imm2, LSL, rm);
571 } else if (bits(op2, 5, 2) == 0xe) {
572 return new %(ldrbt)s(machInst, rt, rn, true, imm8);
573 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
574 const uint32_t puw = bits(machInst, 10, 8);
575 switch (puw) {
576 case 0x1:
577 return new %(ldrb_iw)s(machInst, rt,
578 rn, false, imm8);
579 case 0x3:
580 return new %(ldrb_iuw)s(machInst, rt,
581 rn, true, imm8);
582 case 0x4:
583 return new %(ldrb_ip)s(machInst, rt,
584 rn, false, imm8);
585 case 0x5:
586 return new %(ldrb_ipw)s(machInst, rt,
587 rn, false, imm8);
588 case 0x7:
589 return new %(ldrb_ipuw)s(machInst, rt,
590 rn, true, imm8);
591 }
592 }
593 break;
594 case 0x1:
595 return new %(ldrb_iadd)s(machInst, rt, rn, true, imm12);
596 case 0x2:
597 if (op2 == 0) {
598 return new %(ldrsb_radd)s(machInst, rt, rn, true,
599 imm2, LSL, rm);
600 } else if (bits(op2, 5, 2) == 0xe) {
601 return new %(ldrsbt)s(machInst, rt, rn, true, imm8);
602 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
603 const uint32_t puw = bits(machInst, 10, 8);
604 switch (puw) {
605 case 0x1:
606 return new %(ldrsb_iw)s(machInst, rt,
607 rn, false, imm8);
608 case 0x3:
609 return new %(ldrsb_iuw)s(machInst, rt,
610 rn, true, imm8);
611 case 0x4:
612 return new %(ldrsb_ip)s(machInst, rt,
613 rn, false, imm8);
614 case 0x5:
615 return new %(ldrsb_ipw)s(machInst, rt,
616 rn, false, imm8);
617 case 0x7:
618 return new %(ldrsb_ipuw)s(machInst, rt,
619 rn, true, imm8);
620 }
621 }
622 break;
623 case 0x3:
624 return new %(ldrsb_iadd)s(machInst, rt, rn, true, imm12);
625 }
626 return new Unknown(machInst);
627 }
628 }
629 '''
630 substDict = {
631 "ldrsb_lit_u" : loadImmClassName(False, True, False, 1, True),
632 "ldrsb_lit" : loadImmClassName(False, False, False, 1, True),
633 "ldrb_lit_u" : loadImmClassName(False, True, False, 1),
634 "ldrb_lit" : loadImmClassName(False, False, False, 1),
635 "ldrsb_radd" : loadRegClassName(False, True, False, 1, True),
636 "ldrb_radd" : loadRegClassName(False, True, False, 1),
637 "ldrsb_iw" : loadImmClassName(True, False, True, 1, True),
638 "ldrsb_iuw" : loadImmClassName(True, True, True, 1, True),
639 "ldrsb_ip" : loadImmClassName(False, False, False, 1, True),
640 "ldrsb_ipw" : loadImmClassName(False, False, True, 1, True),
641 "ldrsb_ipuw" : loadImmClassName(False, True, True, 1, True),
642 "ldrsb_iadd" : loadImmClassName(False, True, False, 1, True),
643 "ldrb_iw" : loadImmClassName(True, False, True, 1),
644 "ldrb_iuw" : loadImmClassName(True, True, True, 1),
645 "ldrb_ip" : loadImmClassName(False, False, False, 1),
646 "ldrb_ipw" : loadImmClassName(False, False, True, 1),
647 "ldrb_ipuw" : loadImmClassName(False, True, True, 1),
648 "ldrb_iadd" : loadImmClassName(False, True, False, 1),
649 "ldrbt" : loadImmClassName(False, True, False, 1, user=True),
650 "ldrsbt" : loadImmClassName(False, True, False, 1, True, user=True),
651 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
652 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
653 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
654 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
655 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
656 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
657 "pld_iulit" : "PLD_" + loadImmClassName(False, True, False, 1),
658 "pld_ilit" : "PLD_" + loadImmClassName(False, False, False, 1),
659 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1),
660 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1),
661 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
662 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1),
663 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1)
664 }
665 decode_block = decode % substDict
666}};
667
471def format LoadHalfwordMemoryHints() {{
472 decode = '''
473 {
474 const uint32_t op1 = bits(machInst, 24, 23);
475 const uint32_t op2 = bits(machInst, 11, 6);
476 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
477 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
478 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);

--- 268 unchanged lines hidden --- 		668def format LoadHalfwordMemoryHints() {{
669 decode = '''
670 {
671 const uint32_t op1 = bits(machInst, 24, 23);
672 const uint32_t op2 = bits(machInst, 11, 6);
673 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
674 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
675 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);

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