mem.isa (7246:e366ee883a74) mem.isa (7277:85e4f11ad2c3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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463 "str_imm" : storeImmClassName(False, True, False),
464 "str_puw" : buildPuwDecode(4),
465 "strt" : storeImmClassName(False, True, False, user=True),
466 "str_reg" : storeRegClassName(False, True, False)
467 }
468 decode_block = decode % classNames
469}};
470
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 454 unchanged lines hidden (view full) ---

463 "str_imm" : storeImmClassName(False, True, False),
464 "str_puw" : buildPuwDecode(4),
465 "strt" : storeImmClassName(False, True, False, user=True),
466 "str_reg" : storeRegClassName(False, True, False)
467 }
468 decode_block = decode % classNames
469}};
470
471def format LoadHalfwordMemoryHints() {{
472 decode = '''
473 {
474 const uint32_t op1 = bits(machInst, 24, 23);
475 const uint32_t op2 = bits(machInst, 11, 6);
476 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
477 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
478 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
479 const uint32_t imm12 = bits(machInst, 11, 0);
480 const uint32_t imm8 = bits(machInst, 7, 0);
481 bool pldw = bits(machInst, 21);
482 const uint32_t imm2 = bits(machInst, 5, 4);
483 if (rn == 0xf) {
484 if (rt == 0xf) {
485 if (bits(op1, 1) == 1) {
486 // Unallocated memory hint
487 return new NopInst(machInst);
488 } else {
489 return new Unknown(machInst);
490 }
491 } else {
492 if (bits(op1, 1) == 1) {
493 if (bits(machInst, 23)) {
494 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC,
495 true, imm12);
496 } else {
497 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC,
498 false, imm12);
499 }
500 } else {
501 if (bits(machInst, 23)) {
502 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC,
503 true, imm12);
504 } else {
505 return new %(ldrh_lit)s(machInst, rt, INTREG_PC,
506 false, imm12);
507 }
508 }
509 }
510 } else if (rt == 0xf) {
511 switch (op1) {
512 case 0x0:
513 if (op2 == 0x0) {
514 if (pldw) {
515 return new %(pldw_radd)s(machInst, INTREG_ZERO,
516 rn, true, imm2, LSL, rm);
517 } else {
518 return new %(pld_radd)s(machInst, INTREG_ZERO,
519 rn, true, imm2, LSL, rm);
520 }
521 } else if (bits(op2, 5, 2) == 0xc) {
522 if (pldw) {
523 return new %(pldw_isub)s(machInst, INTREG_ZERO,
524 rn, false, imm8);
525 } else {
526 return new %(pld_isub)s(machInst, INTREG_ZERO,
527 rn, false, imm8);
528 }
529 }
530 break;
531 case 0x1:
532 if (pldw) {
533 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
534 rn, true, imm12);
535 } else {
536 return new %(pld_iadd)s(machInst, INTREG_ZERO,
537 rn, true, imm12);
538 }
539 case 0x2:
540 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) {
541 // Unallocated memory hint
542 return new NopInst(machInst);
543 }
544 break;
545 case 0x3:
546 return new NopInst(machInst);
547 }
548 return new Unknown(machInst);
549 } else {
550 switch (op1) {
551 case 0x0:
552 if (op2 == 0) {
553 return new %(ldrh_radd)s(machInst, rt, rn, true,
554 imm2, LSL, rm);
555 } else if (bits(op2, 5, 2) == 0xe) {
556 return new %(ldrht)s(machInst, rt, rn, true, imm8);
557 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
558 const uint32_t puw = bits(machInst, 10, 8);
559 switch (puw) {
560 case 0x1:
561 return new %(ldrh_iw)s(machInst, rt,
562 rn, false, imm8);
563 case 0x3:
564 return new %(ldrh_iuw)s(machInst, rt,
565 rn, true, imm8);
566 case 0x4:
567 return new %(ldrh_ip)s(machInst, rt,
568 rn, false, imm8);
569 case 0x5:
570 return new %(ldrh_ipw)s(machInst, rt,
571 rn, false, imm8);
572 case 0x7:
573 return new %(ldrh_ipuw)s(machInst, rt,
574 rn, true, imm8);
575 }
576 }
577 break;
578 case 0x1:
579 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12);
580 case 0x2:
581 if (op2 == 0) {
582 return new %(ldrsh_radd)s(machInst, rt, rn, true,
583 imm2, LSL, rm);
584 } else if (bits(op2, 5, 2) == 0xe) {
585 return new %(ldrsht)s(machInst, rt, rn, true, imm8);
586 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
587 const uint32_t puw = bits(machInst, 10, 8);
588 switch (puw) {
589 case 0x1:
590 return new %(ldrsh_iw)s(machInst, rt,
591 rn, false, imm8);
592 case 0x3:
593 return new %(ldrsh_iuw)s(machInst, rt,
594 rn, true, imm8);
595 case 0x4:
596 return new %(ldrsh_ip)s(machInst, rt,
597 rn, false, imm8);
598 case 0x5:
599 return new %(ldrsh_ipw)s(machInst, rt,
600 rn, false, imm8);
601 case 0x7:
602 return new %(ldrsh_ipuw)s(machInst, rt,
603 rn, true, imm8);
604 }
605 }
606 break;
607 case 0x3:
608 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12);
609 }
610 return new Unknown(machInst);
611 }
612 }
613 '''
614 substDict = {
615 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True),
616 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True),
617 "ldrh_lit_u" : loadImmClassName(False, True, False, 2),
618 "ldrh_lit" : loadImmClassName(False, False, False, 2),
619 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True),
620 "ldrh_radd" : loadRegClassName(False, True, False, 2),
621 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True),
622 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True),
623 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True),
624 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True),
625 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True),
626 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True),
627 "ldrh_iw" : loadImmClassName(True, False, True, 2),
628 "ldrh_iuw" : loadImmClassName(True, True, True, 2),
629 "ldrh_ip" : loadImmClassName(False, False, False, 2),
630 "ldrh_ipw" : loadImmClassName(False, False, True, 2),
631 "ldrh_ipuw" : loadImmClassName(False, True, True, 2),
632 "ldrh_iadd" : loadImmClassName(False, True, False, 2),
633 "ldrht" : loadImmClassName(False, True, False, 2, user=True),
634 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True),
635 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
636 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
637 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
638 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
639 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
640 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1)
641 }
642 decode_block = decode % substDict
643}};
644
471def format Thumb16MemReg() {{
472 decode = '''
473 {
474 const uint32_t opb = bits(machInst, 11, 9);
475 const uint32_t rt = bits(machInst, 2, 0);
476 const uint32_t rn = bits(machInst, 5, 3);
477 const uint32_t rm = bits(machInst, 8, 6);
478 switch (opb) {

--- 94 unchanged lines hidden --- 		645def format Thumb16MemReg() {{
646 decode = '''
647 {
648 const uint32_t opb = bits(machInst, 11, 9);
649 const uint32_t rt = bits(machInst, 2, 0);
650 const uint32_t rn = bits(machInst, 5, 3);
651 const uint32_t rm = bits(machInst, 8, 6);
652 switch (opb) {

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