mem.isa (7126:0f3f378d2b7f) | mem.isa (7129:0eb03024678f) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 24 unchanged lines hidden (view full) --- 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 24 unchanged lines hidden (view full) --- 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// |
41// Authors: Stephen Hines | 41// Authors: Gabe Black 42// Stephen Hines |
42 43//////////////////////////////////////////////////////////////////// 44// 45// Memory-format instructions 46// 47 48def template LoadStoreDeclare {{ 49 /** --- 28 unchanged lines hidden (view full) --- 78def template LoadStoreConstructor {{ 79 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 81 { 82 %(constructor)s; 83 } 84}}; 85 | 43 44//////////////////////////////////////////////////////////////////// 45// 46// Memory-format instructions 47// 48 49def template LoadStoreDeclare {{ 50 /** --- 28 unchanged lines hidden (view full) --- 79def template LoadStoreConstructor {{ 80 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 81 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 82 { 83 %(constructor)s; 84 } 85}}; 86 |
86let {{ 87 def buildPUBWLCase(p, u, b, w, l): 88 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) 89 90 def buildMode3Inst(p, u, i, w, type, code, mnem): 91 op = ("-", "+")[u] 92 offset = ("%s Rm", "%s hilo")[i] % op 93 ea_code = "EA = Rn %s;" % ("", offset)[p] 94 if p == 0 or w == 1: 95 code += "Rn = Rn %s;" % offset 96 newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w) 97 suffix = ("Reg", "Hilo")[i] 98 return LoadStoreBase(mnem, mnem.capitalize() + newSuffix, 99 ea_code, code, mem_flags = [], inst_flags = [], 100 base_class = 'Memory' + suffix, 101 exec_template_base = type.capitalize()) 102}}; 103 | |
104def format AddrMode2(imm) {{ 105 if eval(imm): 106 imm = True 107 else: 108 imm = False 109 | 87def format AddrMode2(imm) {{ 88 if eval(imm): 89 imm = True 90 else: 91 imm = False 92 |
93 def buildPUBWLCase(p, u, b, w, l): 94 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) 95 |
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110 header_output = decoder_output = exec_output = "" 111 decode_block = "switch(PUBWL) {\n" 112 113 # Loop over all the values of p, u, b, w and l and build instructions and 114 # a decode block for them. 115 for p in (0, 1): 116 for u in (0, 1): 117 for b in (0, 1): 118 for w in (0, 1): 119 post = (p == 0) | 96 header_output = decoder_output = exec_output = "" 97 decode_block = "switch(PUBWL) {\n" 98 99 # Loop over all the values of p, u, b, w and l and build instructions and 100 # a decode block for them. 101 for p in (0, 1): 102 for u in (0, 1): 103 for b in (0, 1): 104 for w in (0, 1): 105 post = (p == 0) |
120 user = (p == 0 and w == 0) | 106 user = (p == 0 and w == 1) |
121 writeback = (p == 0 or w == 1) 122 add = (u == 1) 123 if b == 0: 124 size = 4 125 else: 126 size = 1 127 if add: 128 addStr = "true" --- 29 unchanged lines hidden (view full) --- 158 (buildPUBWLCase(p,u,b,w,0), storeDecode) 159 decode_block += ''' 160 default: 161 return new Unknown(machInst); 162 break; 163 }''' 164}}; 165 | 107 writeback = (p == 0 or w == 1) 108 add = (u == 1) 109 if b == 0: 110 size = 4 111 else: 112 size = 1 113 if add: 114 addStr = "true" --- 29 unchanged lines hidden (view full) --- 144 (buildPUBWLCase(p,u,b,w,0), storeDecode) 145 decode_block += ''' 146 default: 147 return new Unknown(machInst); 148 break; 149 }''' 150}}; 151 |
166def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{ 167 l0Code = ArmGenericCodeSubs(l0Code); 168 l1Code = ArmGenericCodeSubs(l1Code); | 152def format AddrMode3() {{ 153 decode = ''' 154 { 155 const uint32_t op1 = bits(machInst, 24, 20); 156 const uint32_t op2 = bits(machInst, 6, 5); 157 const uint32_t puiw = bits(machInst, 24, 21); 158 const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0; 159 switch (op2) { 160 case 0x1: 161 if (op1 & 0x1) { 162 %(ldrh)s 163 } else { 164 %(strh)s 165 } 166 case 0x2: 167 if (op1 & 0x1) { 168 %(ldrsb)s 169 } else { 170 %(ldrd)s 171 } 172 case 0x3: 173 if (op1 & 0x1) { 174 %(ldrsh)s 175 } else { 176 %(strd)s 177 } 178 default: 179 return new Unknown(machInst); 180 } 181 } 182 ''' |
169 | 183 |
170 header_output = decoder_output = exec_output = "" 171 decode_block = "switch(PUBWL) {\n" 172 (l0Mnem, l1Mnem) = name.split("_"); | 184 def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False): 185 post = (p == 0) 186 user = (p == 0 and w == 1) 187 writeback = (p == 0 or w == 1) 188 add = (u == 1) 189 caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0) 190 decode = ''' 191 case %#x: 192 return new '''% caseVal 193 if add: 194 addStr = "true" 195 else: 196 addStr = "false" 197 if i: 198 if load: 199 if d: 200 className = loadDoubleImmClassName(post, add, writeback) 201 else: 202 className = loadImmClassName(post, add, writeback, \ 203 size=size, sign=sign, \ 204 user=user) 205 else: 206 if d: 207 className = storeDoubleImmClassName(post, add, writeback) 208 else: 209 className = storeImmClassName(post, add, writeback, \ 210 size=size, sign=sign, \ 211 user=user) 212 decode += ("%s(machInst, RT, RN, %s, imm);\n" % \ 213 (className, addStr)) 214 else: 215 if load: 216 if d: 217 className = loadDoubleRegClassName(post, add, writeback) 218 else: 219 className = loadRegClassName(post, add, writeback, \ 220 size=size, sign=sign, \ 221 user=user) 222 else: 223 if d: 224 className = storeDoubleRegClassName(post, add, writeback) 225 else: 226 className = storeRegClassName(post, add, writeback, \ 227 size=size, sign=sign, \ 228 user=user) 229 decode += ("%s(machInst, RT, RN, %s, 0, LSL, RM);\n" % \ 230 (className, addStr)) 231 return decode |
173 | 232 |
174 # Loop over all the values of p, u, i, w and l and build instructions and 175 # a decode block for them. 176 for (l, type, code, mnem) in ((0, l0Type, l0Code, l0Mnem), 177 (1, l1Type, l1Code, l1Mnem)): | 233 def decodePuiw(load, d, size=4, sign=False): 234 global decodePuiwCase 235 decode = "switch (puiw) {\n" |
178 for p in (0, 1): | 236 for p in (0, 1): |
179 wset = (0, 1) 180 if (p == 0): 181 wset = (0,) | |
182 for u in (0, 1): 183 for i in (0, 1): | 237 for u in (0, 1): 238 for i in (0, 1): |
184 for w in wset: 185 (new_header_output, 186 new_decoder_output, 187 new_decode_block, 188 new_exec_output) = buildMode3Inst(p, u, i, w, 189 type, code, mnem) 190 header_output += new_header_output 191 decoder_output += new_decoder_output 192 exec_output += new_exec_output 193 decode_block += ''' 194 case %#x: 195 {%s} 196 break; 197 ''' % (buildPUBWLCase(p,u,i,w,l), new_decode_block) | 239 for w in (0, 1): 240 decode += decodePuiwCase(load, d, p, u, i, w, 241 size, sign) 242 decode += ''' 243 default: 244 return new Unknown(machInst); 245 } 246 ''' 247 return decode |
198 | 248 |
199 decode_block += ''' 200 default: 201 return new Unknown(machInst); 202 break; 203 }''' | 249 subs = { 250 "ldrh" : decodePuiw(True, False, size=2), 251 "strh" : decodePuiw(False, False, size=2), 252 "ldrsb" : decodePuiw(True, False, size=1, sign=True), 253 "ldrd" : decodePuiw(True, True), 254 "ldrsh" : decodePuiw(True, False, size=2, sign=True), 255 "strd" : decodePuiw(False, True) 256 } 257 decode_block = decode % subs |
204}}; 205 206def format Thumb32LoadWord() {{ 207 decode = ''' 208 { 209 uint32_t op1 = bits(machInst, 24, 23); 210 if (bits(op1, 1) == 0) { 211 uint32_t op2 = bits(machInst, 11, 6); --- 270 unchanged lines hidden --- | 258}}; 259 260def format Thumb32LoadWord() {{ 261 decode = ''' 262 { 263 uint32_t op1 = bits(machInst, 24, 23); 264 if (bits(op1, 1) == 0) { 265 uint32_t op2 = bits(machInst, 11, 6); --- 270 unchanged lines hidden --- |