mem.isa (7124:50d26210c812) | mem.isa (7125:212ad902f257) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 384 unchanged lines hidden (view full) --- 393 "ldr" : loadRegClassName(False, True, False), 394 "ldrh" : loadRegClassName(False, True, False, size=2), 395 "ldrb" : loadRegClassName(False, True, False, size=1), 396 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2), 397 } 398 decode_block = decode % classNames 399}}; 400 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 384 unchanged lines hidden (view full) --- 393 "ldr" : loadRegClassName(False, True, False), 394 "ldrh" : loadRegClassName(False, True, False, size=2), 395 "ldrb" : loadRegClassName(False, True, False, size=1), 396 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2), 397 } 398 decode_block = decode % classNames 399}}; 400 |
401def format Thumb16MemImm() {{ 402 decode = ''' 403 { 404 const uint32_t opa = bits(machInst, 15, 12); 405 const uint32_t opb = bits(machInst, 11, 9); 406 const uint32_t lrt = bits(machInst, 2, 0); 407 const uint32_t lrn = bits(machInst, 5, 3); 408 const uint32_t hrt = bits(machInst, 10, 8); 409 const uint32_t imm5 = bits(machInst, 10, 6); 410 const uint32_t imm8 = bits(machInst, 7, 0); 411 const bool load = bits(opb, 2); 412 switch (opa) { 413 case 0x6: 414 if (load) { 415 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2); 416 } else { 417 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2); 418 } 419 case 0x7: 420 if (load) { 421 return new %(ldrb)s(machInst, lrt, lrn, true, imm5); 422 } else { 423 return new %(strb)s(machInst, lrt, lrn, true, imm5); 424 } 425 case 0x8: 426 if (load) { 427 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1); 428 } else { 429 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1); 430 } 431 case 0x9: 432 if (load) { 433 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 434 } else { 435 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 436 } 437 default: 438 return new Unknown(machInst); 439 } 440 } 441 ''' 442 classNames = { 443 "ldr" : loadImmClassName(False, True, False), 444 "str" : storeImmClassName(False, True, False), 445 "ldrh" : loadImmClassName(False, True, False, size=2), 446 "strh" : storeImmClassName(False, True, False, size=2), 447 "ldrb" : loadImmClassName(False, True, False, size=1), 448 "strb" : storeImmClassName(False, True, False, size=1), 449 } 450 decode_block = decode % classNames 451}}; 452 |
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401def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, 402 mem_flags = [], inst_flags = []) {{ 403 ea_code = ArmGenericCodeSubs(ea_code) 404 memacc_code = ArmGenericCodeSubs(memacc_code) 405 (header_output, decoder_output, decode_block, exec_output) = \ 406 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 407 decode_template = BasicDecode, 408 exec_template_base = 'Load') 409}}; 410 411def format ArmStoreMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, 412 mem_flags = [], inst_flags = []) {{ 413 ea_code = ArmGenericCodeSubs(ea_code) 414 memacc_code = ArmGenericCodeSubs(memacc_code) 415 (header_output, decoder_output, decode_block, exec_output) = \ 416 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 417 exec_template_base = 'Store') 418}}; 419 | 453def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, 454 mem_flags = [], inst_flags = []) {{ 455 ea_code = ArmGenericCodeSubs(ea_code) 456 memacc_code = ArmGenericCodeSubs(memacc_code) 457 (header_output, decoder_output, decode_block, exec_output) = \ 458 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 459 decode_template = BasicDecode, 460 exec_template_base = 'Load') 461}}; 462 463def format ArmStoreMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, 464 mem_flags = [], inst_flags = []) {{ 465 ea_code = ArmGenericCodeSubs(ea_code) 466 memacc_code = ArmGenericCodeSubs(memacc_code) 467 (header_output, decoder_output, decode_block, exec_output) = \ 468 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 469 exec_template_base = 'Store') 470}}; 471 |