mem.isa (7119:5ad962dec52f) mem.isa (7120:d630089169f3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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78def template LoadStoreConstructor {{
79 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
81 {
82 %(constructor)s;
83 }
84}};
85
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 69 unchanged lines hidden (view full) ---

78def template LoadStoreConstructor {{
79 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
81 {
82 %(constructor)s;
83 }
84}};
85
86
87def template StoreExecute {{
88 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
89 Trace::InstRecord *traceData) const
90 {
91 Addr EA;
92 Fault fault = NoFault;
93
94 %(op_decl)s;
95 %(op_rd)s;
96 %(ea_code)s;
97
98 if (%(predicate_test)s)
99 {
100 if (fault == NoFault) {
101 %(memacc_code)s;
102 }
103
104 if (fault == NoFault) {
105 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
106 memAccessFlags, NULL);
107 }
108
109 if (fault == NoFault) {
110 %(op_wb)s;
111 }
112 }
113
114 return fault;
115 }
116}};
117
118def template StoreInitiateAcc {{
119 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
120 Trace::InstRecord *traceData) const
121 {
122 Addr EA;
123 Fault fault = NoFault;
124
125 %(op_decl)s;
126 %(op_rd)s;
127 %(ea_code)s;
128
129 if (%(predicate_test)s)
130 {
131 if (fault == NoFault) {
132 %(memacc_code)s;
133 }
134
135 if (fault == NoFault) {
136 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
137 memAccessFlags, NULL);
138 }
139
140 // Need to write back any potential address register update
141 if (fault == NoFault) {
142 %(op_wb)s;
143 }
144 }
145
146 return fault;
147 }
148}};
149
150
151def template StoreCompleteAcc {{
152 Fault %(class_name)s::completeAcc(PacketPtr pkt,
153 %(CPU_exec_context)s *xc,
154 Trace::InstRecord *traceData) const
155 {
156 Fault fault = NoFault;
157
158 %(op_decl)s;
159 %(op_rd)s;
160
161 if (%(predicate_test)s)
162 {
163 if (fault == NoFault) {
164 %(op_wb)s;
165 }
166 }
167
168 return fault;
169 }
170}};
171
172def template StoreCondCompleteAcc {{
173 Fault %(class_name)s::completeAcc(PacketPtr pkt,
174 %(CPU_exec_context)s *xc,
175 Trace::InstRecord *traceData) const
176 {
177 Fault fault = NoFault;
178
179 %(op_dest_decl)s;
180
181 if (%(predicate_test)s)
182 {
183 if (fault == NoFault) {
184 %(op_wb)s;
185 }
186 }
187
188 return fault;
189 }
190}};
191
192let {{
193 def buildPUBWLCase(p, u, b, w, l):
194 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
195
86let {{
87 def buildPUBWLCase(p, u, b, w, l):
88 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
89
196 def buildMode2Inst(p, u, b, w, l, suffix, offset):
197 mnem = ("str", "ldr")[l]
198 op = ("-", "+")[u]
199 offset = op + ArmGenericCodeSubs(offset);
200 mem = ("Mem", "Mem.ub")[b]
201 code = ("%s = Rd;", "Rd = %s;")[l] % mem
202 ea_code = "EA = Rn %s;" % ("", offset)[p]
203 if p == 0 or w == 1:
204 code += "Rn = Rn %s;" % offset
205 if p == 0 and w == 0:
206 # Here's where we'll tack on a flag to make this a usermode access.
207 mnem += "t"
208 type = ("Store", "Load")[l]
209 newSuffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w)
210 if b == 1:
211 mnem += "b"
212 return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
213 ea_code, code, mem_flags = [], inst_flags = [],
214 base_class = 'Memory' + suffix,
215 exec_template_base = type.capitalize())
216
217 def buildMode3Inst(p, u, i, w, type, code, mnem):
218 op = ("-", "+")[u]
219 offset = ("%s Rm", "%s hilo")[i] % op
220 ea_code = "EA = Rn %s;" % ("", offset)[p]
221 if p == 0 or w == 1:
222 code += "Rn = Rn %s;" % offset
223 newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w)
224 suffix = ("Reg", "Hilo")[i]
225 return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
226 ea_code, code, mem_flags = [], inst_flags = [],
227 base_class = 'Memory' + suffix,
228 exec_template_base = type.capitalize())
229}};
230
90 def buildMode3Inst(p, u, i, w, type, code, mnem):
91 op = ("-", "+")[u]
92 offset = ("%s Rm", "%s hilo")[i] % op
93 ea_code = "EA = Rn %s;" % ("", offset)[p]
94 if p == 0 or w == 1:
95 code += "Rn = Rn %s;" % offset
96 newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w)
97 suffix = ("Reg", "Hilo")[i]
98 return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
99 ea_code, code, mem_flags = [], inst_flags = [],
100 base_class = 'Memory' + suffix,
101 exec_template_base = type.capitalize())
102}};
103
231def format AddrMode2(imm, suffix, offset) {{
104def format AddrMode2(imm) {{
232 if eval(imm):
233 imm = True
234 else:
235 imm = False
236
237 header_output = decoder_output = exec_output = ""
238 decode_block = "switch(PUBWL) {\n"
239
240 # Loop over all the values of p, u, b, w and l and build instructions and
241 # a decode block for them.
242 for p in (0, 1):
243 for u in (0, 1):
244 for b in (0, 1):
245 for w in (0, 1):
105 if eval(imm):
106 imm = True
107 else:
108 imm = False
109
110 header_output = decoder_output = exec_output = ""
111 decode_block = "switch(PUBWL) {\n"
112
113 # Loop over all the values of p, u, b, w and l and build instructions and
114 # a decode block for them.
115 for p in (0, 1):
116 for u in (0, 1):
117 for b in (0, 1):
118 for w in (0, 1):
246 (new_header_output,
247 new_decoder_output,
248 new_decode_block,
249 new_exec_output) = buildMode2Inst(p, u, b, w, 0,
250 suffix, offset)
251 header_output += new_header_output
252 decoder_output += new_decoder_output
253 exec_output += new_exec_output
254 decode_block += '''
255 case %#x:
256 {%s}
257 break;
258 ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)
259
260 post = (p == 0)
261 user = (p == 0 and w == 0)
262 writeback = (p == 0 or w == 1)
263 add = (u == 1)
264 if b == 0:
265 size = 4
266 else:
267 size = 1
268 if add:
269 addStr = "true"
270 else:
271 addStr = "false"
272 if imm:
273 newDecode = "return new %s(machInst, RD, RN," + \
274 "%s, machInst.immed11_0);"
119 post = (p == 0)
120 user = (p == 0 and w == 0)
121 writeback = (p == 0 or w == 1)
122 add = (u == 1)
123 if b == 0:
124 size = 4
125 else:
126 size = 1
127 if add:
128 addStr = "true"
129 else:
130 addStr = "false"
131 if imm:
132 newDecode = "return new %s(machInst, RD, RN," + \
133 "%s, machInst.immed11_0);"
275 className = loadImmClassName(post, add, writeback,
134 loadClass = loadImmClassName(post, add, writeback,
276 size, False, user)
135 size, False, user)
277 newDecode = newDecode % (className, addStr)
136 storeClass = storeImmClassName(post, add, writeback,
137 size, False, user)
138 loadDecode = newDecode % (loadClass, addStr)
139 storeDecode = newDecode % (storeClass, addStr)
278 else:
279 newDecode = "return new %s(machInst, RD, RN, %s," + \
280 "machInst.shiftSize," + \
281 "machInst.shift, RM);"
140 else:
141 newDecode = "return new %s(machInst, RD, RN, %s," + \
142 "machInst.shiftSize," + \
143 "machInst.shift, RM);"
282 className = loadRegClassName(post, add, writeback,
144 loadClass = loadRegClassName(post, add, writeback,
283 size, False, user)
145 size, False, user)
284 newDecode = newDecode % (className, addStr)
285 decode_block += '''
146 storeClass = storeRegClassName(post, add, writeback,
147 size, False, user)
148 loadDecode = newDecode % (loadClass, addStr)
149 storeDecode = newDecode % (storeClass, addStr)
150 decode = '''
286 case %#x:
287 {%s}
288 break;
151 case %#x:
152 {%s}
153 break;
289 ''' % (buildPUBWLCase(p,u,b,w,1), newDecode)
154 '''
155 decode_block += decode % \
156 (buildPUBWLCase(p,u,b,w,1), loadDecode)
157 decode_block += decode % \
158 (buildPUBWLCase(p,u,b,w,0), storeDecode)
290 decode_block += '''
291 default:
292 return new Unknown(machInst);
293 break;
294 }'''
295}};
296
297def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{

--- 58 unchanged lines hidden --- 		159 decode_block += '''
160 default:
161 return new Unknown(machInst);
162 break;
163 }'''
164}};
165
166def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{

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