mem.isa (6303:cb190056165e) mem.isa (6305:e518d78b2ed1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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34//
35
36def template LoadStoreDeclare {{
37 /**
38 * Static instruction class for "%(mnemonic)s".
39 */
40 class %(class_name)s : public %(base_class)s
41 {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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34//
35
36def template LoadStoreDeclare {{
37 /**
38 * Static instruction class for "%(mnemonic)s".
39 */
40 class %(class_name)s : public %(base_class)s
41 {
42 protected:
43
44 /**
45 * "Fake" effective address computation class for "%(mnemonic)s".
46 */
47 class EAComp : public %(base_class)s
48 {
49 public:
50 /// Constructor
51 EAComp(ExtMachInst machInst);
52
53 %(BasicExecDeclare)s
54 };
55
56 /**
57 * "Fake" memory access instruction class for "%(mnemonic)s".
58 */
59 class MemAcc : public %(base_class)s
60 {
61 public:
62 /// Constructor
63 MemAcc(ExtMachInst machInst);
64
65 %(BasicExecDeclare)s
66 };
67
68 public:
69
70 /// Constructor.
71 %(class_name)s(ExtMachInst machInst);
72
73 %(BasicExecDeclare)s
74
75 %(InitiateAccDeclare)s

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84}};
85
86
87def template CompleteAccDeclare {{
88 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
89}};
90
91
42 public:
43
44 /// Constructor.
45 %(class_name)s(ExtMachInst machInst);
46
47 %(BasicExecDeclare)s
48
49 %(InitiateAccDeclare)s

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58}};
59
60
61def template CompleteAccDeclare {{
62 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
63}};
64
65
92def template EACompConstructor {{
93 inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
94 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
95 {
96 %(constructor)s;
97 }
98}};
99
100
101def template MemAccConstructor {{
102 inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
103 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
104 {
105 %(constructor)s;
106 }
107}};
108
109
110def template LoadStoreConstructor {{
111 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
66def template LoadStoreConstructor {{
67 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
112 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
113 new EAComp(machInst), new MemAcc(machInst))
68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
114 {
115 %(constructor)s;
116 }
117}};
118
119
69 {
70 %(constructor)s;
71 }
72}};
73
74
120def template EACompExecute {{
121 Fault
122 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
123 Trace::InstRecord *traceData) const
124 {
125 Addr EA;
126 Fault fault = NoFault;
127
128 %(op_decl)s;
129 %(op_rd)s;
130 %(ea_code)s;
131
132 if (%(predicate_test)s)
133 {
134 if (fault == NoFault) {
135 %(op_wb)s;
136 xc->setEA(EA);
137 }
138 }
139
140 return fault;
141 }
142}};
143
144def template LoadMemAccExecute {{
145 Fault
146 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
147 Trace::InstRecord *traceData) const
148 {
149 Addr EA;
150 Fault fault = NoFault;
151
152 %(op_decl)s;
153 %(op_rd)s;
154 EA = xc->getEA();
155
156 if (%(predicate_test)s)
157 {
158 if (fault == NoFault) {
159 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
160 %(memacc_code)s;
161 }
162
163 if (fault == NoFault) {
164 %(op_wb)s;
165 }
166 }
167
168 return fault;
169 }
170}};
171
172
173def template LoadExecute {{
174 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
175 Trace::InstRecord *traceData) const
176 {
177 Addr EA;
178 Fault fault = NoFault;
179
180 %(op_decl)s;

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245 }
246 }
247
248 return fault;
249 }
250}};
251
252
75def template LoadExecute {{
76 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
77 Trace::InstRecord *traceData) const
78 {
79 Addr EA;
80 Fault fault = NoFault;
81
82 %(op_decl)s;

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147 }
148 }
149
150 return fault;
151 }
152}};
153
154
253def template StoreMemAccExecute {{
254 Fault
255 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
256 Trace::InstRecord *traceData) const
257 {
258 Addr EA;
259 Fault fault = NoFault;
260
261 %(op_decl)s;
262 %(op_rd)s;
263
264 if (%(predicate_test)s)
265 {
266 EA = xc->getEA();
267
268 if (fault == NoFault) {
269 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
270 memAccessFlags, NULL);
271 if (traceData) { traceData->setData(Mem); }
272 }
273
274 if (fault == NoFault) {
275 %(op_wb)s;
276 }
277 }
278
279 return fault;
280 }
281}};
282
283
284def template StoreExecute {{
285 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
286 Trace::InstRecord *traceData) const
287 {
288 Addr EA;
289 Fault fault = NoFault;
290
291 %(op_decl)s;

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383 %(op_wb)s;
384 }
385 }
386
387 return fault;
388 }
389}};
390
155def template StoreExecute {{
156 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
157 Trace::InstRecord *traceData) const
158 {
159 Addr EA;
160 Fault fault = NoFault;
161
162 %(op_decl)s;

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254 %(op_wb)s;
255 }
256 }
257
258 return fault;
259 }
260}};
261
391
392def template MiscMemAccExecute {{
393 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
394 Trace::InstRecord *traceData) const
395 {
396 Addr EA;
397 Fault fault = NoFault;
398
399 %(op_decl)s;
400 %(op_rd)s;
401
402 if (%(predicate_test)s)
403 {
404 EA = xc->getEA();
405
406 if (fault == NoFault) {
407 %(memacc_code)s;
408 }
409 }
410
411 return NoFault;
412 }
413}};
414
415def template MiscExecute {{
416 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
417 Trace::InstRecord *traceData) const
418 {
419 Addr EA;
420 Fault fault = NoFault;
421
422 %(op_decl)s;
423 %(op_rd)s;
424 %(ea_code)s;
425
426 if (%(predicate_test)s)
427 {
428 if (fault == NoFault) {
429 %(memacc_code)s;
430 }
431 }
432
433 return NoFault;
434 }
435}};
436
437def template MiscInitiateAcc {{
438 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
439 Trace::InstRecord *traceData) const
440 {
441 panic("Misc instruction does not support split access method!");
442 return NoFault;
443 }
444}};
445
446
447def template MiscCompleteAcc {{
448 Fault %(class_name)s::completeAcc(PacketPtr pkt,
449 %(CPU_exec_context)s *xc,
450 Trace::InstRecord *traceData) const
451 {
452 panic("Misc instruction does not support split access method!");
453
454 return NoFault;
455 }
456}};
457
458let {{
459 def buildPUBWLCase(p, u, b, w, l):
460 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
461
462 def buildMode2Inst(p, u, b, w, l, suffix, offset):
463 mnem = ("str", "ldr")[l]
464 op = ("-", "+")[u]
465 offset = op + ArmGenericCodeSubs(offset);

--- 118 unchanged lines hidden --- 		262let {{
263 def buildPUBWLCase(p, u, b, w, l):
264 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
265
266 def buildMode2Inst(p, u, b, w, l, suffix, offset):
267 mnem = ("str", "ldr")[l]
268 op = ("-", "+")[u]
269 offset = op + ArmGenericCodeSubs(offset);

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