mem.isa (6241:29c1cc8075e4) mem.isa (6242:1cee707c1228)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 202 unchanged lines hidden (view full) ---

211 Addr EA;
212 Fault fault = NoFault;
213
214 %(fp_enable_check)s;
215 %(op_decl)s;
216 %(op_rd)s;
217 %(ea_code)s;
218
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 202 unchanged lines hidden (view full) ---

211 Addr EA;
212 Fault fault = NoFault;
213
214 %(fp_enable_check)s;
215 %(op_decl)s;
216 %(op_rd)s;
217 %(ea_code)s;
218
219 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
219 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
220 {
221 if (fault == NoFault) {
222 %(op_wb)s;
223 xc->setEA(EA);
224 }
225 }
226
227 return fault;

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236 Addr EA;
237 Fault fault = NoFault;
238
239 %(fp_enable_check)s;
240 %(op_decl)s;
241 %(op_rd)s;
242 EA = xc->getEA();
243
220 {
221 if (fault == NoFault) {
222 %(op_wb)s;
223 xc->setEA(EA);
224 }
225 }
226
227 return fault;

--- 8 unchanged lines hidden (view full) ---

236 Addr EA;
237 Fault fault = NoFault;
238
239 %(fp_enable_check)s;
240 %(op_decl)s;
241 %(op_rd)s;
242 EA = xc->getEA();
243
244 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
244 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
245 {
246 if (fault == NoFault) {
247 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
248 %(memacc_code)s;
249 }
250
251 if (fault == NoFault) {
252 %(op_wb)s;

--- 12 unchanged lines hidden (view full) ---

265 Addr EA;
266 Fault fault = NoFault;
267
268 %(fp_enable_check)s;
269 %(op_decl)s;
270 %(op_rd)s;
271 %(ea_code)s;
272
245 {
246 if (fault == NoFault) {
247 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
248 %(memacc_code)s;
249 }
250
251 if (fault == NoFault) {
252 %(op_wb)s;

--- 12 unchanged lines hidden (view full) ---

265 Addr EA;
266 Fault fault = NoFault;
267
268 %(fp_enable_check)s;
269 %(op_decl)s;
270 %(op_rd)s;
271 %(ea_code)s;
272
273 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
273 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
274 {
275 if (fault == NoFault) {
276 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
277 %(memacc_code)s;
278 }
279
280 if (fault == NoFault) {
281 %(op_wb)s;

--- 12 unchanged lines hidden (view full) ---

294 Addr EA;
295 Fault fault = NoFault;
296
297 %(fp_enable_check)s;
298 %(op_src_decl)s;
299 %(op_rd)s;
300 %(ea_code)s;
301
274 {
275 if (fault == NoFault) {
276 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
277 %(memacc_code)s;
278 }
279
280 if (fault == NoFault) {
281 %(op_wb)s;

--- 12 unchanged lines hidden (view full) ---

294 Addr EA;
295 Fault fault = NoFault;
296
297 %(fp_enable_check)s;
298 %(op_src_decl)s;
299 %(op_rd)s;
300 %(ea_code)s;
301
302 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
302 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
303 {
304 if (fault == NoFault) {
305 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
306 }
307 }
308
309 return fault;
310 }

--- 6 unchanged lines hidden (view full) ---

317 Trace::InstRecord *traceData) const
318 {
319 Fault fault = NoFault;
320
321 %(fp_enable_check)s;
322 %(op_decl)s;
323 %(op_rd)s;
324
303 {
304 if (fault == NoFault) {
305 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
306 }
307 }
308
309 return fault;
310 }

--- 6 unchanged lines hidden (view full) ---

317 Trace::InstRecord *traceData) const
318 {
319 Fault fault = NoFault;
320
321 %(fp_enable_check)s;
322 %(op_decl)s;
323 %(op_rd)s;
324
325 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
325 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
326 {
327 // ARM instructions will not have a pkt if the predicate is false
328 Mem = pkt->get<typeof(Mem)>();
329
330 if (fault == NoFault) {
331 %(memacc_code)s;
332 }
333

--- 14 unchanged lines hidden (view full) ---

348 {
349 Addr EA;
350 Fault fault = NoFault;
351
352 %(fp_enable_check)s;
353 %(op_decl)s;
354 %(op_rd)s;
355
326 {
327 // ARM instructions will not have a pkt if the predicate is false
328 Mem = pkt->get<typeof(Mem)>();
329
330 if (fault == NoFault) {
331 %(memacc_code)s;
332 }
333

--- 14 unchanged lines hidden (view full) ---

348 {
349 Addr EA;
350 Fault fault = NoFault;
351
352 %(fp_enable_check)s;
353 %(op_decl)s;
354 %(op_rd)s;
355
356 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
356 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
357 {
358 EA = xc->getEA();
359
360 if (fault == NoFault) {
361 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
362 memAccessFlags, NULL);
363 if (traceData) { traceData->setData(Mem); }
364 }

--- 15 unchanged lines hidden (view full) ---

380 Addr EA;
381 Fault fault = NoFault;
382
383 %(fp_enable_check)s;
384 %(op_decl)s;
385 %(op_rd)s;
386 %(ea_code)s;
387
357 {
358 EA = xc->getEA();
359
360 if (fault == NoFault) {
361 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
362 memAccessFlags, NULL);
363 if (traceData) { traceData->setData(Mem); }
364 }

--- 15 unchanged lines hidden (view full) ---

380 Addr EA;
381 Fault fault = NoFault;
382
383 %(fp_enable_check)s;
384 %(op_decl)s;
385 %(op_rd)s;
386 %(ea_code)s;
387
388 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
388 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
389 {
390 if (fault == NoFault) {
391 %(memacc_code)s;
392 }
393
394 if (fault == NoFault) {
395 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
396 memAccessFlags, NULL);

--- 16 unchanged lines hidden (view full) ---

413 Addr EA;
414 Fault fault = NoFault;
415
416 %(fp_enable_check)s;
417 %(op_decl)s;
418 %(op_rd)s;
419 %(ea_code)s;
420
389 {
390 if (fault == NoFault) {
391 %(memacc_code)s;
392 }
393
394 if (fault == NoFault) {
395 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
396 memAccessFlags, NULL);

--- 16 unchanged lines hidden (view full) ---

413 Addr EA;
414 Fault fault = NoFault;
415
416 %(fp_enable_check)s;
417 %(op_decl)s;
418 %(op_rd)s;
419 %(ea_code)s;
420
421 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
421 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
422 {
423 if (fault == NoFault) {
424 %(memacc_code)s;
425 }
426
427 if (fault == NoFault) {
428 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
429 memAccessFlags, NULL);

--- 16 unchanged lines hidden (view full) ---

446 %(CPU_exec_context)s *xc,
447 Trace::InstRecord *traceData) const
448 {
449 Fault fault = NoFault;
450
451 %(fp_enable_check)s;
452 %(op_dest_decl)s;
453
422 {
423 if (fault == NoFault) {
424 %(memacc_code)s;
425 }
426
427 if (fault == NoFault) {
428 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
429 memAccessFlags, NULL);

--- 16 unchanged lines hidden (view full) ---

446 %(CPU_exec_context)s *xc,
447 Trace::InstRecord *traceData) const
448 {
449 Fault fault = NoFault;
450
451 %(fp_enable_check)s;
452 %(op_dest_decl)s;
453
454 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
454 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
455 {
456 if (fault == NoFault) {
457 %(op_wb)s;
458 }
459 }
460
461 return fault;
462 }

--- 4 unchanged lines hidden (view full) ---

467 %(CPU_exec_context)s *xc,
468 Trace::InstRecord *traceData) const
469 {
470 Fault fault = NoFault;
471
472 %(fp_enable_check)s;
473 %(op_dest_decl)s;
474
455 {
456 if (fault == NoFault) {
457 %(op_wb)s;
458 }
459 }
460
461 return fault;
462 }

--- 4 unchanged lines hidden (view full) ---

467 %(CPU_exec_context)s *xc,
468 Trace::InstRecord *traceData) const
469 {
470 Fault fault = NoFault;
471
472 %(fp_enable_check)s;
473 %(op_dest_decl)s;
474
475 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
475 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
476 {
477 if (fault == NoFault) {
478 %(op_wb)s;
479 }
480 }
481
482 return fault;
483 }

--- 6 unchanged lines hidden (view full) ---

490 {
491 Addr EA;
492 Fault fault = NoFault;
493
494 %(fp_enable_check)s;
495 %(op_decl)s;
496 %(op_rd)s;
497
476 {
477 if (fault == NoFault) {
478 %(op_wb)s;
479 }
480 }
481
482 return fault;
483 }

--- 6 unchanged lines hidden (view full) ---

490 {
491 Addr EA;
492 Fault fault = NoFault;
493
494 %(fp_enable_check)s;
495 %(op_decl)s;
496 %(op_rd)s;
497
498 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
498 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
499 {
500 EA = xc->getEA();
501
502 if (fault == NoFault) {
503 %(memacc_code)s;
504 }
505 }
506

--- 8 unchanged lines hidden (view full) ---

515 Addr EA;
516 Fault fault = NoFault;
517
518 %(fp_enable_check)s;
519 %(op_decl)s;
520 %(op_rd)s;
521 %(ea_code)s;
522
499 {
500 EA = xc->getEA();
501
502 if (fault == NoFault) {
503 %(memacc_code)s;
504 }
505 }
506

--- 8 unchanged lines hidden (view full) ---

515 Addr EA;
516 Fault fault = NoFault;
517
518 %(fp_enable_check)s;
519 %(op_decl)s;
520 %(op_rd)s;
521 %(ea_code)s;
522
523 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
523 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
524 {
525 if (fault == NoFault) {
526 %(memacc_code)s;
527 }
528 }
529
530 return NoFault;
531 }

--- 42 unchanged lines hidden --- 		524 {
525 if (fault == NoFault) {
526 %(memacc_code)s;
527 }
528 }
529
530 return NoFault;
531 }

--- 42 unchanged lines hidden ---