mem.isa (13587:9d4da35335af) | mem.isa (13589:13522f2a5126) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010 ARM Limited | 3// Copyright (c) 2010,2019 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 208 unchanged lines hidden (view full) --- 220}}; 221 222def format ArmSyncMem() {{ 223 decode_block = ''' 224 { 225 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 226 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 227 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 208 unchanged lines hidden (view full) --- 220}}; 221 222def format ArmSyncMem() {{ 223 decode_block = ''' 224 { 225 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 226 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 227 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); |
228 switch (PUBWL) { 229 case 0x18: | 228 229 const auto type_L = bits(machInst, 22, 20); 230 const auto ex_ord = bits(machInst, 9, 8); 231 const auto dec_fields = (type_L << 2) | ex_ord; 232 233 switch (dec_fields) { 234 case 0x00: 235 return new %(stl)s(machInst, rt, rn, true, 0); 236 case 0x02: 237 return new %(stlex)s(machInst, rt, rt2, rn, true, 0); 238 case 0x03: |
230 return new %(strex)s(machInst, rt, rt2, rn, true, 0); | 239 return new %(strex)s(machInst, rt, rt2, rn, true, 0); |
231 case 0x19: | 240 case 0x04: 241 return new %(lda)s(machInst, rt, rn, true, 0); 242 case 0x06: 243 return new %(ldaex)s(machInst, rt, rn, true, 0); 244 case 0x07: |
232 return new %(ldrex)s(machInst, rt, rn, true, 0); | 245 return new %(ldrex)s(machInst, rt, rn, true, 0); |
233 case 0x1a: | 246 case 0x0a: 247 return new %(stlexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0); 248 case 0x0b: |
234 return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0); | 249 return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0); |
235 case 0x1b: | 250 case 0x0e: 251 return new %(ldaexd)s(machInst, rt, rt + 1, rn, true, 0); 252 case 0x0f: |
236 return new %(ldrexd)s(machInst, rt, rt + 1, rn, true, 0); | 253 return new %(ldrexd)s(machInst, rt, rt + 1, rn, true, 0); |
237 case 0x1c: | 254 case 0x10: 255 return new %(stlb)s(machInst, rt, rn, true, 0); 256 case 0x12: 257 return new %(stlexb)s(machInst, rt, rt2, rn, true, 0); 258 case 0x13: |
238 return new %(strexb)s(machInst, rt, rt2, rn, true, 0); | 259 return new %(strexb)s(machInst, rt, rt2, rn, true, 0); |
239 case 0x1d: | 260 case 0x14: 261 return new %(ldab)s(machInst, rt, rn, true, 0); 262 case 0x16: 263 return new %(ldaexb)s(machInst, rt, rn, true, 0); 264 case 0x17: |
240 return new %(ldrexb)s(machInst, rt, rn, true, 0); | 265 return new %(ldrexb)s(machInst, rt, rn, true, 0); |
241 case 0x1e: | 266 case 0x18: 267 return new %(stlh)s(machInst, rt, rn, true, 0); 268 case 0x1a: 269 return new %(stlexh)s(machInst, rt, rt2, rn, true, 0); 270 case 0x1b: |
242 return new %(strexh)s(machInst, rt, rt2, rn, true, 0); | 271 return new %(strexh)s(machInst, rt, rt2, rn, true, 0); |
272 case 0x1c: 273 return new %(ldah)s(machInst, rt, rn, true, 0); 274 case 0x1e: 275 return new %(ldaexh)s(machInst, rt, rn, true, 0); |
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243 case 0x1f: 244 return new %(ldrexh)s(machInst, rt, rn, true, 0); 245 default: 246 return new Unknown(machInst); 247 } 248 } 249 ''' % { 250 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 251 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 252 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 253 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 254 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 255 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 256 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), | 276 case 0x1f: 277 return new %(ldrexh)s(machInst, rt, rn, true, 0); 278 default: 279 return new Unknown(machInst); 280 } 281 } 282 ''' % { 283 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 284 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 285 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 286 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 287 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 288 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 289 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), |
257 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False) | 290 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False), 291 292 "lda" : "LDA_" + loadImmClassName(False, True, False, size=4), 293 "ldab" : "LDAB_" + loadImmClassName(False, True, False, size=1), 294 "ldah" : "LDAH_" + loadImmClassName(False, True, False, size=2), 295 "ldaex" : "LDAEX_" + loadImmClassName(False, True, False, size=4), 296 "ldaexb" : "LDAEXB_" + loadImmClassName(False, True, False, size=1), 297 "ldaexh" : "LDAEXH_" + loadImmClassName(False, True, False, size=2), 298 "ldaexd" : "LDAEXD_" + loadDoubleImmClassName(False, True, False), 299 300 "stl" : "STL_" + storeImmClassName(False, True, False, size=4), 301 "stlb" : "STLB_" + storeImmClassName(False, True, False, size=1), 302 "stlh" : "STLH_" + storeImmClassName(False, True, False, size=2), 303 "stlex" : "STLEX_" + storeImmClassName(False, True, False, size=4), 304 "stlexb" : "STLEXB_" + storeImmClassName(False, True, False, size=1), 305 "stlexh" : "STLEXH_" + storeImmClassName(False, True, False, size=2), 306 "stlexd" : "STLEXD_" + storeDoubleImmClassName(False, True, False) |
258 } 259}}; 260 261def format Thumb32SrsRfe() {{ 262 decode_block = ''' 263 { 264 const bool wb = (bits(machInst, 21) == 1); 265 const bool add = (bits(machInst, 24, 23) == 0x3); --- 70 unchanged lines hidden (view full) --- 336 switch (op3) { 337 case 0x4: 338 return new %(strexb)s(machInst, rd, rt, rn, true, 0); 339 case 0x5: 340 return new %(strexh)s(machInst, rd, rt, rn, true, 0); 341 case 0x7: 342 return new %(strexd)s(machInst, rd, rt, 343 rt2, rn, true, 0); | 307 } 308}}; 309 310def format Thumb32SrsRfe() {{ 311 decode_block = ''' 312 { 313 const bool wb = (bits(machInst, 21) == 1); 314 const bool add = (bits(machInst, 24, 23) == 0x3); --- 70 unchanged lines hidden (view full) --- 385 switch (op3) { 386 case 0x4: 387 return new %(strexb)s(machInst, rd, rt, rn, true, 0); 388 case 0x5: 389 return new %(strexh)s(machInst, rd, rt, rn, true, 0); 390 case 0x7: 391 return new %(strexd)s(machInst, rd, rt, 392 rt2, rn, true, 0); |
393 case 0x8: 394 return new %(stlb)s(machInst, rt, rn, true, 0); 395 case 0x9: 396 return new %(stlh)s(machInst, rt, rn, true, 0); 397 case 0xa: 398 return new %(stl)s(machInst, rt, rn, true, 0); 399 case 0xc: 400 return new %(stlexb)s(machInst, rd, rt, rn, true, 0); 401 case 0xd: 402 return new %(stlexh)s(machInst, rd, rt, rn, true, 0); 403 case 0xe: 404 return new %(stlex)s(machInst, rd, rt, rn, true, 0); 405 case 0xf: 406 return new %(stlexd)s(machInst, rd, rt, 407 rt2, rn, true, 0); |
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344 default: 345 return new Unknown(machInst); 346 } 347 } else { 348 switch (op3) { 349 case 0x0: 350 return new Tbb(machInst, rn, rd); 351 case 0x1: 352 return new Tbh(machInst, rn, rd); 353 case 0x4: 354 return new %(ldrexb)s(machInst, rt, rn, true, 0); 355 case 0x5: 356 return new %(ldrexh)s(machInst, rt, rn, true, 0); 357 case 0x7: 358 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0); | 408 default: 409 return new Unknown(machInst); 410 } 411 } else { 412 switch (op3) { 413 case 0x0: 414 return new Tbb(machInst, rn, rd); 415 case 0x1: 416 return new Tbh(machInst, rn, rd); 417 case 0x4: 418 return new %(ldrexb)s(machInst, rt, rn, true, 0); 419 case 0x5: 420 return new %(ldrexh)s(machInst, rt, rn, true, 0); 421 case 0x7: 422 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0); |
423 case 0x8: 424 return new %(ldab)s(machInst, rt, rn, true, 0); 425 case 0x9: 426 return new %(ldah)s(machInst, rt, rn, true, 0); 427 case 0xa: 428 return new %(lda)s(machInst, rt, rn, true, 0); 429 case 0xc: 430 return new %(ldaexb)s(machInst, rt, rn, true, 0); 431 case 0xd: 432 return new %(ldaexh)s(machInst, rt, rn, true, 0); 433 case 0xe: 434 return new %(ldaex)s(machInst, rt, rn, true, 0); 435 case 0xf: 436 return new %(ldaexd)s(machInst, rt, rt2, rn, true, 0); |
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359 default: 360 return new Unknown(machInst); 361 } 362 } 363 } 364 } else { 365 const uint32_t puw = (bits(machInst, 24, 23) << 1) | 366 bits(machInst, 21); --- 50 unchanged lines hidden (view full) --- 417 "ldrd_pw" : loadDoubleImmClassName(False, False, True), 418 "ldrd_pu" : loadDoubleImmClassName(False, True, False), 419 "ldrd_puw" : loadDoubleImmClassName(False, True, True), 420 "strd_w" : storeDoubleImmClassName(True, False, True), 421 "strd_uw" : storeDoubleImmClassName(True, True, True), 422 "strd_p" : storeDoubleImmClassName(False, False, False), 423 "strd_pw" : storeDoubleImmClassName(False, False, True), 424 "strd_pu" : storeDoubleImmClassName(False, True, False), | 437 default: 438 return new Unknown(machInst); 439 } 440 } 441 } 442 } else { 443 const uint32_t puw = (bits(machInst, 24, 23) << 1) | 444 bits(machInst, 21); --- 50 unchanged lines hidden (view full) --- 495 "ldrd_pw" : loadDoubleImmClassName(False, False, True), 496 "ldrd_pu" : loadDoubleImmClassName(False, True, False), 497 "ldrd_puw" : loadDoubleImmClassName(False, True, True), 498 "strd_w" : storeDoubleImmClassName(True, False, True), 499 "strd_uw" : storeDoubleImmClassName(True, True, True), 500 "strd_p" : storeDoubleImmClassName(False, False, False), 501 "strd_pw" : storeDoubleImmClassName(False, False, True), 502 "strd_pu" : storeDoubleImmClassName(False, True, False), |
425 "strd_puw" : storeDoubleImmClassName(False, True, True) | 503 "strd_puw" : storeDoubleImmClassName(False, True, True), 504 505 "stl" : "STL_" + storeImmClassName(False, True, False, size=4), 506 "stlh" : "STLH_" + storeImmClassName(False, True, False, size=2), 507 "stlb" : "STLB_" + storeImmClassName(False, True, False, size=1), 508 "stlex" : "STLEX_" + storeImmClassName(False, True, False, size=4), 509 "stlexh" : "STLEXH_" + storeImmClassName(False, True, False, size=2), 510 "stlexb" : "STLEXB_" + storeImmClassName(False, True, False, size=1), 511 "stlexd" : "STLEXD_" + storeDoubleImmClassName(False, True, False), 512 "lda" : "LDA_" + loadImmClassName(False, True, False, size=4), 513 "ldah" : "LDAH_" + loadImmClassName(False, True, False, size=2), 514 "ldab" : "LDAB_" + loadImmClassName(False, True, False, size=1), 515 "ldaex" : "LDAEX_" + loadImmClassName(False, True, False, size=4), 516 "ldaexh" : "LDAEXH_" + loadImmClassName(False, True, False, size=2), 517 "ldaexb" : "LDAEXB_" + loadImmClassName(False, True, False, size=1), 518 "ldaexd" : "LDAEXD_" + loadDoubleImmClassName(False, True, False) |
426 } 427}}; 428 429def format Thumb32LoadWord() {{ 430 decode = ''' 431 { 432 uint32_t op1 = bits(machInst, 24, 23); 433 if (bits(op1, 1) == 0) { --- 631 unchanged lines hidden --- | 519 } 520}}; 521 522def format Thumb32LoadWord() {{ 523 decode = ''' 524 { 525 uint32_t op1 = bits(machInst, 24, 23); 526 if (bits(op1, 1) == 0) { --- 631 unchanged lines hidden --- |