1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 254 unchanged lines hidden (view full) --- 263 "imm_p" : loadImmClassName(False, False, False), 264 "imm_pw" : loadImmClassName(False, False, True), 265 "imm_pu" : loadImmClassName(False, True, False), 266 "imm_puw" : loadImmClassName(False, True, True) 267 } 268 decode_block = decode % classNames 269}}; 270 |
271def format Thumb32StoreSingle() {{ 272 def buildPuwDecode(size): 273 puwDecode = ''' 274 { 275 uint32_t puw = bits(machInst, 10, 8); 276 uint32_t imm = IMMED_7_0; 277 switch (puw) { 278 case 0: 279 case 2: 280 // If we're here, either P or W must have been set. 281 panic("Neither P or W set, but that " 282 "shouldn't be possible.\\n"); 283 case 1: 284 return new %(imm_w)s(machInst, RT, RN, false, imm); 285 case 3: 286 return new %(imm_uw)s(machInst, RT, RN, true, imm); 287 case 4: 288 return new %(imm_p)s(machInst, RT, RN, false, imm); 289 case 5: 290 return new %(imm_pw)s(machInst, RT, RN, false, imm); 291 case 6: 292 return new %(imm_pu)s(machInst, RT, RN, true, imm); 293 case 7: 294 return new %(imm_puw)s(machInst, RT, RN, true, imm); 295 } 296 } 297 ''' 298 return puwDecode % { 299 "imm_w" : storeImmClassName(True, False, True, size=size), 300 "imm_uw" : storeImmClassName(True, True, True, size=size), 301 "imm_p" : storeImmClassName(False, False, False, size=size), 302 "imm_pw" : storeImmClassName(False, False, True, size=size), 303 "imm_pu" : storeImmClassName(False, True, False, size=size), 304 "imm_puw" : storeImmClassName(False, True, True, size=size) 305 } 306 decode = ''' 307 { 308 uint32_t op1 = bits(machInst, 23, 21); 309 uint32_t op2 = bits(machInst, 11, 6); 310 bool op2Puw = ((op2 & 0x24) == 0x24 || 311 (op2 & 0x3c) == 0x30); 312 if (op1 == 4) { 313 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0); 314 } else if (op1 == 0 && op2Puw) { 315 %(strb_puw)s; 316 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) { 317 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0); 318 } else if (op1 == 0 && op2 == 0) { 319 return new %(strb_reg)s(machInst, RT, RN, true, 320 bits(machInst, 5, 4), LSL, RM); 321 } else if (op1 == 5) { 322 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0); 323 } else if (op1 == 1 && op2Puw) { 324 %(strh_puw)s; 325 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) { 326 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0); 327 } else if (op1 == 1 && op2 == 0) { 328 return new %(strh_reg)s(machInst, RT, RN, true, 329 bits(machInst, 5, 4), LSL, RM); 330 } else if (op1 == 6) { 331 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0); 332 } else if (op1 == 2 && op2Puw) { 333 %(str_puw)s; 334 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) { 335 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0); 336 } else if (op1 == 2 && op2 == 0) { 337 return new %(str_reg)s(machInst, RT, RN, true, 338 bits(machInst, 5, 4), LSL, RM); 339 } else { 340 return new Unknown(machInst); 341 } 342 } 343 ''' 344 classNames = { 345 "strb_imm" : storeImmClassName(False, True, False, size=1), 346 "strb_puw" : buildPuwDecode(1), 347 "strbt" : storeImmClassName(False, True, False, user=True, size=1), 348 "strb_reg" : storeRegClassName(False, True, False, size=1), 349 "strh_imm" : storeImmClassName(False, True, False, size=2), 350 "strh_puw" : buildPuwDecode(2), 351 "strht" : storeImmClassName(False, True, False, user=True, size=2), 352 "strh_reg" : storeRegClassName(False, True, False, size=2), 353 "str_imm" : storeImmClassName(False, True, False), 354 "str_puw" : buildPuwDecode(4), 355 "strt" : storeImmClassName(False, True, False, user=True), 356 "str_reg" : storeRegClassName(False, True, False) 357 } 358 decode_block = decode % classNames 359}}; 360 |
361def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, 362 mem_flags = [], inst_flags = []) {{ 363 ea_code = ArmGenericCodeSubs(ea_code) 364 memacc_code = ArmGenericCodeSubs(memacc_code) 365 (header_output, decoder_output, decode_block, exec_output) = \ 366 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 367 decode_template = BasicDecode, 368 exec_template_base = 'Load') 369}}; 370 371def format ArmStoreMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, 372 mem_flags = [], inst_flags = []) {{ 373 ea_code = ArmGenericCodeSubs(ea_code) 374 memacc_code = ArmGenericCodeSubs(memacc_code) 375 (header_output, decoder_output, decode_block, exec_output) = \ 376 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 377 exec_template_base = 'Store') 378}}; 379 |