1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// |
15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright --- 56 unchanged lines hidden (view full) --- 79 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 81 { 82 %(constructor)s; 83 } 84}}; 85 86 |
87def template StoreExecute {{ 88 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 89 Trace::InstRecord *traceData) const 90 { 91 Addr EA; 92 Fault fault = NoFault; 93 94 %(op_decl)s; --- 128 unchanged lines hidden (view full) --- 223 newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w) 224 suffix = ("Reg", "Hilo")[i] 225 return LoadStoreBase(mnem, mnem.capitalize() + newSuffix, 226 ea_code, code, mem_flags = [], inst_flags = [], 227 base_class = 'Memory' + suffix, 228 exec_template_base = type.capitalize()) 229}}; 230 |
231def format AddrMode2(imm, suffix, offset) {{ 232 if eval(imm): 233 imm = True 234 else: 235 imm = False 236 |
237 header_output = decoder_output = exec_output = "" 238 decode_block = "switch(PUBWL) {\n" 239 240 # Loop over all the values of p, u, b, w and l and build instructions and 241 # a decode block for them. 242 for p in (0, 1): 243 for u in (0, 1): 244 for b in (0, 1): 245 for w in (0, 1): |
246 (new_header_output, 247 new_decoder_output, 248 new_decode_block, 249 new_exec_output) = buildMode2Inst(p, u, b, w, 0, 250 suffix, offset) 251 header_output += new_header_output 252 decoder_output += new_decoder_output 253 exec_output += new_exec_output 254 decode_block += ''' 255 case %#x: 256 {%s} 257 break; 258 ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block) 259 260 post = (p == 0) 261 user = (p == 0 and w == 0) 262 writeback = (p == 0 or w == 1) 263 add = (u == 1) 264 if b == 0: 265 size = 4 266 else: 267 size = 1 268 if add: 269 addStr = "true" 270 else: 271 addStr = "false" 272 if imm: 273 newDecode = "return new %s(machInst, RD, RN," + \ 274 "%s, machInst.immed11_0);" 275 className = loadImmClassName(post, add, writeback, 276 size, False, user) 277 newDecode = newDecode % (className, addStr) 278 else: 279 newDecode = "return new %s(machInst, RD, RN, %s," + \ 280 "machInst.shiftSize," + \ 281 "machInst.shift, RM);" 282 className = loadRegClassName(post, add, writeback, 283 size, False, user) 284 newDecode = newDecode % (className, addStr) 285 decode_block += ''' 286 case %#x: 287 {%s} 288 break; 289 ''' % (buildPUBWLCase(p,u,b,w,1), newDecode) |
290 decode_block += ''' 291 default: 292 return new Unknown(machInst); 293 break; 294 }''' 295}}; 296 297def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{ --- 58 unchanged lines hidden --- |