86,191d85
<
< def template StoreExecute {{
< Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
< Trace::InstRecord *traceData) const
< {
< Addr EA;
< Fault fault = NoFault;
<
< %(op_decl)s;
< %(op_rd)s;
< %(ea_code)s;
<
< if (%(predicate_test)s)
< {
< if (fault == NoFault) {
< %(memacc_code)s;
< }
<
< if (fault == NoFault) {
< fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
< memAccessFlags, NULL);
< }
<
< if (fault == NoFault) {
< %(op_wb)s;
< }
< }
<
< return fault;
< }
< }};
<
< def template StoreInitiateAcc {{
< Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
< Trace::InstRecord *traceData) const
< {
< Addr EA;
< Fault fault = NoFault;
<
< %(op_decl)s;
< %(op_rd)s;
< %(ea_code)s;
<
< if (%(predicate_test)s)
< {
< if (fault == NoFault) {
< %(memacc_code)s;
< }
<
< if (fault == NoFault) {
< fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
< memAccessFlags, NULL);
< }
<
< // Need to write back any potential address register update
< if (fault == NoFault) {
< %(op_wb)s;
< }
< }
<
< return fault;
< }
< }};
<
<
< def template StoreCompleteAcc {{
< Fault %(class_name)s::completeAcc(PacketPtr pkt,
< %(CPU_exec_context)s *xc,
< Trace::InstRecord *traceData) const
< {
< Fault fault = NoFault;
<
< %(op_decl)s;
< %(op_rd)s;
<
< if (%(predicate_test)s)
< {
< if (fault == NoFault) {
< %(op_wb)s;
< }
< }
<
< return fault;
< }
< }};
<
< def template StoreCondCompleteAcc {{
< Fault %(class_name)s::completeAcc(PacketPtr pkt,
< %(CPU_exec_context)s *xc,
< Trace::InstRecord *traceData) const
< {
< Fault fault = NoFault;
<
< %(op_dest_decl)s;
<
< if (%(predicate_test)s)
< {
< if (fault == NoFault) {
< %(op_wb)s;
< }
< }
<
< return fault;
< }
< }};
<
196,216d89
< def buildMode2Inst(p, u, b, w, l, suffix, offset):
< mnem = ("str", "ldr")[l]
< op = ("-", "+")[u]
< offset = op + ArmGenericCodeSubs(offset);
< mem = ("Mem", "Mem.ub")[b]
< code = ("%s = Rd;", "Rd = %s;")[l] % mem
< ea_code = "EA = Rn %s;" % ("", offset)[p]
< if p == 0 or w == 1:
< code += "Rn = Rn %s;" % offset
< if p == 0 and w == 0:
< # Here's where we'll tack on a flag to make this a usermode access.
< mnem += "t"
< type = ("Store", "Load")[l]
< newSuffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w)
< if b == 1:
< mnem += "b"
< return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
< ea_code, code, mem_flags = [], inst_flags = [],
< base_class = 'Memory' + suffix,
< exec_template_base = type.capitalize())
<
231c104
< def format AddrMode2(imm, suffix, offset) {{
---
> def format AddrMode2(imm) {{
246,259d118
< (new_header_output,
< new_decoder_output,
< new_decode_block,
< new_exec_output) = buildMode2Inst(p, u, b, w, 0,
< suffix, offset)
< header_output += new_header_output
< decoder_output += new_decoder_output
< exec_output += new_exec_output
< decode_block += '''
< case %#x:
< {%s}
< break;
< ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)
<
275c134
< className = loadImmClassName(post, add, writeback,
---
> loadClass = loadImmClassName(post, add, writeback,
277c136,139
< newDecode = newDecode % (className, addStr)
---
> storeClass = storeImmClassName(post, add, writeback,
> size, False, user)
> loadDecode = newDecode % (loadClass, addStr)
> storeDecode = newDecode % (storeClass, addStr)
282c144
< className = loadRegClassName(post, add, writeback,
---
> loadClass = loadRegClassName(post, add, writeback,
284,285c146,150
< newDecode = newDecode % (className, addStr)
< decode_block += '''
---
> storeClass = storeRegClassName(post, add, writeback,
> size, False, user)
> loadDecode = newDecode % (loadClass, addStr)
> storeDecode = newDecode % (storeClass, addStr)
> decode = '''
289c154,158
< ''' % (buildPUBWLCase(p,u,b,w,1), newDecode)
---
> '''
> decode_block += decode % \
> (buildPUBWLCase(p,u,b,w,1), loadDecode)
> decode_block += decode % \
> (buildPUBWLCase(p,u,b,w,0), storeDecode)