2a3,14
> // Copyright (c) 2010 ARM Limited
> // All rights reserved
> //
> // The license below extends only to copyright in the software and shall
> // not be construed as granting a license to any other intellectual
> // property including but not limited to intellectual property relating
> // to a hardware implementation of the functionality of the software
> // licensed hereunder. You may use the software subject to the license
> // terms below provided that you ensure that this notice is replicated
> // unmodified and in its entirety in all distributions of the software,
> // modified or unmodified, in source code or in binary form.
> //
75,154d86
< def template LoadExecute {{
< Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
< Trace::InstRecord *traceData) const
< {
< Addr EA;
< Fault fault = NoFault;
<
< %(op_decl)s;
< %(op_rd)s;
< %(ea_code)s;
<
< if (%(predicate_test)s)
< {
< if (fault == NoFault) {
< fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
< %(memacc_code)s;
< }
<
< if (fault == NoFault) {
< %(op_wb)s;
< }
< }
<
< return fault;
< }
< }};
<
<
< def template LoadInitiateAcc {{
< Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
< Trace::InstRecord *traceData) const
< {
< Addr EA;
< Fault fault = NoFault;
<
< %(op_src_decl)s;
< %(op_rd)s;
< %(ea_code)s;
<
< if (%(predicate_test)s)
< {
< if (fault == NoFault) {
< fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
< }
< }
<
< return fault;
< }
< }};
<
<
< def template LoadCompleteAcc {{
< Fault %(class_name)s::completeAcc(PacketPtr pkt,
< %(CPU_exec_context)s *xc,
< Trace::InstRecord *traceData) const
< {
< Fault fault = NoFault;
<
< %(op_decl)s;
< %(op_rd)s;
<
< if (%(predicate_test)s)
< {
< // ARM instructions will not have a pkt if the predicate is false
< Mem = pkt->get<typeof(Mem)>();
<
< if (fault == NoFault) {
< %(memacc_code)s;
< }
<
< if (fault == NoFault) {
< %(op_wb)s;
< }
< }
<
< return fault;
< }
< }};
<
<
299c231,236
< def format AddrMode2(suffix, offset) {{
---
> def format AddrMode2(imm, suffix, offset) {{
> if eval(imm):
> imm = True
> else:
> imm = False
>
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< for l in (0, 1):
< (new_header_output,
< new_decoder_output,
< new_decode_block,
< new_exec_output) = buildMode2Inst(p, u, b, w, l,
< suffix, offset)
< header_output += new_header_output
< decoder_output += new_decoder_output
< exec_output += new_exec_output
< decode_block += '''
< case %#x:
< {%s}
< break;
< ''' % (buildPUBWLCase(p,u,b,w,l), new_decode_block)
---
> (new_header_output,
> new_decoder_output,
> new_decode_block,
> new_exec_output) = buildMode2Inst(p, u, b, w, 0,
> suffix, offset)
> header_output += new_header_output
> decoder_output += new_decoder_output
> exec_output += new_exec_output
> decode_block += '''
> case %#x:
> {%s}
> break;
> ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)
>
> post = (p == 0)
> user = (p == 0 and w == 0)
> writeback = (p == 0 or w == 1)
> add = (u == 1)
> if b == 0:
> size = 4
> else:
> size = 1
> if add:
> addStr = "true"
> else:
> addStr = "false"
> if imm:
> newDecode = "return new %s(machInst, RD, RN," + \
> "%s, machInst.immed11_0);"
> className = loadImmClassName(post, add, writeback,
> size, False, user)
> newDecode = newDecode % (className, addStr)
> else:
> newDecode = "return new %s(machInst, RD, RN, %s," + \
> "machInst.shiftSize," + \
> "machInst.shift, RM);"
> className = loadRegClassName(post, add, writeback,
> size, False, user)
> newDecode = newDecode % (className, addStr)
> decode_block += '''
> case %#x:
> {%s}
> break;
> ''' % (buildPUBWLCase(p,u,b,w,1), newDecode)