1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Gabe Black
42
43def format AddrMode2(imm) {{
44 if eval(imm):
45 imm = True
46 else:
47 imm = False
48
49 def buildPUBWLCase(p, u, b, w, l):
50 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
51
52 header_output = decoder_output = exec_output = ""
53 decode_block = "switch(PUBWL) {\n"
54
55 # Loop over all the values of p, u, b, w and l and build instructions and
56 # a decode block for them.
57 for p in (0, 1):
58 for u in (0, 1):
59 for b in (0, 1):
60 for w in (0, 1):
61 post = (p == 0)
62 user = (p == 0 and w == 1)
63 writeback = (p == 0 or w == 1)
64 add = (u == 1)
65 if b == 0:
66 size = 4
67 else:
68 size = 1
69 if add:
70 addStr = "true"
71 else:
72 addStr = "false"
73 if imm:
74 newDecode = "return new %s(machInst, RD, RN," + \
75 "%s, machInst.immed11_0);"
76 loadClass = loadImmClassName(post, add, writeback,
77 size, False, user)
78 storeClass = storeImmClassName(post, add, writeback,
79 size, False, user)
80 loadDecode = newDecode % (loadClass, addStr)
81 storeDecode = newDecode % (storeClass, addStr)
82 else:
83 newDecode = "return new %s(machInst, RD, RN, %s," + \
84 "machInst.shiftSize," + \
85 "machInst.shift, RM);"
86 loadClass = loadRegClassName(post, add, writeback,
87 size, False, user)
88 storeClass = storeRegClassName(post, add, writeback,
89 size, False, user)
90 loadDecode = newDecode % (loadClass, addStr)
91 storeDecode = newDecode % (storeClass, addStr)
92 decode = '''
93 case %#x:
94 {%s}
95 break;
96 '''
97 decode_block += decode % \
98 (buildPUBWLCase(p,u,b,w,1), loadDecode)
99 decode_block += decode % \
100 (buildPUBWLCase(p,u,b,w,0), storeDecode)
101 decode_block += '''
102 default:
103 return new Unknown(machInst);
104 break;
105 }'''
106}};
107
108def format AddrMode3() {{
109 decode = '''
110 {
111 const uint32_t op1 = bits(machInst, 24, 20);
112 const uint32_t op2 = bits(machInst, 6, 5);
113 const uint32_t puiw = bits(machInst, 24, 21);
114 const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0;
115 switch (op2) {
116 case 0x1:
117 if (op1 & 0x1) {
118 %(ldrh)s
119 } else {
120 %(strh)s
121 }
122 case 0x2:
123 if (op1 & 0x1) {
124 %(ldrsb)s
125 } else {
126 %(ldrd)s
127 }
128 case 0x3:
129 if (op1 & 0x1) {
130 %(ldrsh)s
131 } else {
132 %(strd)s
133 }
134 default:
135 return new Unknown(machInst);
136 }
137 }
138 '''
139
140 def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False):
141 post = (p == 0)
142 user = (p == 0 and w == 1)
143 writeback = (p == 0 or w == 1)
144 add = (u == 1)
145 caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0)
146 decode = '''
147 case %#x:
148 return new '''% caseVal
149 if add:
150 addStr = "true"
151 else:
152 addStr = "false"
153 if i:
154 if load:
155 if d:
156 className = loadDoubleImmClassName(post, add, writeback)
157 else:
158 className = loadImmClassName(post, add, writeback, \
159 size=size, sign=sign, \
160 user=user)
161 else:
162 if d:
163 className = storeDoubleImmClassName(post, add, writeback)
164 else:
165 className = storeImmClassName(post, add, writeback, \
166 size=size, sign=sign, \
167 user=user)
168 decode += ("%s(machInst, RT, RN, %s, imm);\n" % \
169 (className, addStr))
170 else:
171 if load:
172 if d:
173 className = loadDoubleRegClassName(post, add, writeback)
174 else:
175 className = loadRegClassName(post, add, writeback, \
176 size=size, sign=sign, \
177 user=user)
178 else:
179 if d:
180 className = storeDoubleRegClassName(post, add, writeback)
181 else:
182 className = storeRegClassName(post, add, writeback, \
183 size=size, sign=sign, \
184 user=user)
185 decode += ("%s(machInst, RT, RN, %s, 0, LSL, RM);\n" % \
186 (className, addStr))
187 return decode
188
189 def decodePuiw(load, d, size=4, sign=False):
190 global decodePuiwCase
191 decode = "switch (puiw) {\n"
192 for p in (0, 1):
193 for u in (0, 1):
194 for i in (0, 1):
195 for w in (0, 1):
196 decode += decodePuiwCase(load, d, p, u, i, w,
197 size, sign)
198 decode += '''
199 default:
200 return new Unknown(machInst);
201 }
202 '''
203 return decode
204
205 subs = {
206 "ldrh" : decodePuiw(True, False, size=2),
207 "strh" : decodePuiw(False, False, size=2),
208 "ldrsb" : decodePuiw(True, False, size=1, sign=True),
209 "ldrd" : decodePuiw(True, True),
210 "ldrsh" : decodePuiw(True, False, size=2, sign=True),
211 "strd" : decodePuiw(False, True)
212 }
213 decode_block = decode % subs
214}};
215
216def format ArmSyncMem() {{
217 decode_block = '''
218 {
219 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
220 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
221 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
222 switch (PUBWL) {
223 case 0x10:
224 return new Swp(machInst, rt, rt2, rn);
225 case 0x14:
226 return new Swpb(machInst, rt, rt2, rn);
227 case 0x18:
228 return new WarnUnimplemented("strex", machInst);
229 case 0x19:
230 return new %(ldrex)s(machInst, rt, rn, true, 0);
231 case 0x1a:
232 return new WarnUnimplemented("strexd", machInst);
233 case 0x1b:
234 return new WarnUnimplemented("ldrexd", machInst);
235 case 0x1c:
236 return new WarnUnimplemented("strexb", machInst);
237 case 0x1d:
238 return new %(ldrexb)s(machInst, rt, rn, true, 0);
239 case 0x1e:
240 return new WarnUnimplemented("strexh", machInst);
241 case 0x1f:
242 return new %(ldrexh)s(machInst, rt, rn, true, 0);
243 default:
244 return new Unknown(machInst);
245 }
246 }
247 ''' % {
248 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
249 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
250 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2)
251 }
252}};
253
254def format Thumb32LdrStrDExTbh() {{
255 decode_block = '''
256 {
257 const uint32_t op1 = bits(machInst, 24, 23);
258 const uint32_t op2 = bits(machInst, 21, 20);
259 const uint32_t op3 = bits(machInst, 7, 4);
260 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
261 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
262 /* This isn't used yet, and that makes gcc upset. */
263 //const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
264 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
265 if (op1 == 0) {
266 const uint32_t imm = bits(machInst, 7, 0) << 2;
267 if (op2 == 0) {
268 return new WarnUnimplemented("strex", machInst);
269 } else {
270 return new %(ldrex)s(machInst, rt, rn, true, imm);
271 }
272 } else {
273 if (op2 == 0) {
274 switch (op3) {
275 case 0x4:
276 return new WarnUnimplemented("strexb", machInst);
277 case 0x5:
278 return new WarnUnimplemented("strexh", machInst);
279 case 0x7:
280 return new WarnUnimplemented("strexd", machInst);
281 default:
282 return new Unknown(machInst);
283 }
284 } else {
285 switch (op3) {
286 case 0x0:
287 return new WarnUnimplemented("tbb", machInst);
288 case 0x1:
289 return new WarnUnimplemented("tbh", machInst);
290 case 0x4:
291 return new %(ldrexb)s(machInst, rt, rn, true, 0);
292 case 0x5:
293 return new %(ldrexh)s(machInst, rt, rn, true, 0);
294 case 0x7:
295 return new WarnUnimplemented("ldrexd", machInst);
296 default:
297 return new Unknown(machInst);
298 }
299 }
300 }
301 } else {
302 if (bits(op2, 0) == 0) {
303 return new WarnUnimplemented("strd", machInst);
304 } else {
305 return new WarnUnimplemented("ldrd", machInst);
306 }
307 }
308 }
309 ''' % {
310 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
311 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
312 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2)
313 }
314}};
315
316def format Thumb32LoadWord() {{
317 decode = '''
318 {
319 uint32_t op1 = bits(machInst, 24, 23);
320 if (bits(op1, 1) == 0) {
321 uint32_t op2 = bits(machInst, 11, 6);
322 if (HTRN == 0xF) {
323 if (UP) {
324 return new %(literal_u)s(machInst, RT, INTREG_PC,
325 true, IMMED_11_0);
326 } else {
327 return new %(literal)s(machInst, RT, INTREG_PC,
328 false, IMMED_11_0);
329 }
330 } else if (op1 == 0x1) {
331 return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0);
332 } else if (op2 == 0) {
333 return new %(register)s(machInst, RT, RN, UP,
334 bits(machInst, 5, 4), LSL, RM);
335 } else if ((op2 & 0x3c) == 0x38) {
336 return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0);
337 } else if ((op2 & 0x3c) == 0x30 || //P
338 (op2 & 0x24) == 0x24) { //W
339 uint32_t puw = bits(machInst, 10, 8);
340 uint32_t imm = IMMED_7_0;
341 switch (puw) {
342 case 0:
343 case 2:
344 // If we're here, either P or W must have been set.
345 panic("Neither P or W set, but that "
346 "shouldn't be possible.\\n");
347 case 1:
348 return new %(imm_w)s(machInst, RT, RN, false, imm);
349 case 3:
350 return new %(imm_uw)s(machInst, RT, RN, true, imm);
351 case 4:
352 return new %(imm_p)s(machInst, RT, RN, false, imm);
353 case 5:
354 return new %(imm_pw)s(machInst, RT, RN, false, imm);
355 case 6:
356 return new %(imm_pu)s(machInst, RT, RN, true, imm);
357 case 7:
358 return new %(imm_puw)s(machInst, RT, RN, true, imm);
359 }
360 }
361 } else {
362 return new Unknown(machInst);
363 }
364 }
365 '''
366 classNames = {
367 "literal_u" : loadImmClassName(False, True, False),
368 "literal" : loadImmClassName(False, False, False),
369 "register" : loadRegClassName(False, True, False),
370 "ldrt" : loadImmClassName(False, True, False, user=True),
371 "imm_w" : loadImmClassName(True, False, True),
372 "imm_uw" : loadImmClassName(True, True, True),
373 "imm_p" : loadImmClassName(False, False, False),
374 "imm_pw" : loadImmClassName(False, False, True),
375 "imm_pu" : loadImmClassName(False, True, False),
376 "imm_puw" : loadImmClassName(False, True, True)
377 }
378 decode_block = decode % classNames
379}};
380
381def format Thumb32StoreSingle() {{
382 def buildPuwDecode(size):
383 puwDecode = '''
384 {
385 uint32_t puw = bits(machInst, 10, 8);
386 uint32_t imm = IMMED_7_0;
387 switch (puw) {
388 case 0:
389 case 2:
390 // If we're here, either P or W must have been set.
391 panic("Neither P or W set, but that "
392 "shouldn't be possible.\\n");
393 case 1:
394 return new %(imm_w)s(machInst, RT, RN, false, imm);
395 case 3:
396 return new %(imm_uw)s(machInst, RT, RN, true, imm);
397 case 4:
398 return new %(imm_p)s(machInst, RT, RN, false, imm);
399 case 5:
400 return new %(imm_pw)s(machInst, RT, RN, false, imm);
401 case 6:
402 return new %(imm_pu)s(machInst, RT, RN, true, imm);
403 case 7:
404 return new %(imm_puw)s(machInst, RT, RN, true, imm);
405 }
406 }
407 '''
408 return puwDecode % {
409 "imm_w" : storeImmClassName(True, False, True, size=size),
410 "imm_uw" : storeImmClassName(True, True, True, size=size),
411 "imm_p" : storeImmClassName(False, False, False, size=size),
412 "imm_pw" : storeImmClassName(False, False, True, size=size),
413 "imm_pu" : storeImmClassName(False, True, False, size=size),
414 "imm_puw" : storeImmClassName(False, True, True, size=size)
415 }
416 decode = '''
417 {
418 uint32_t op1 = bits(machInst, 23, 21);
419 uint32_t op2 = bits(machInst, 11, 6);
420 bool op2Puw = ((op2 & 0x24) == 0x24 ||
421 (op2 & 0x3c) == 0x30);
422 if (op1 == 4) {
423 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0);
424 } else if (op1 == 0 && op2Puw) {
425 %(strb_puw)s;
426 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) {
427 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0);
428 } else if (op1 == 0 && op2 == 0) {
429 return new %(strb_reg)s(machInst, RT, RN, true,
430 bits(machInst, 5, 4), LSL, RM);
431 } else if (op1 == 5) {
432 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0);
433 } else if (op1 == 1 && op2Puw) {
434 %(strh_puw)s;
435 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) {
436 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0);
437 } else if (op1 == 1 && op2 == 0) {
438 return new %(strh_reg)s(machInst, RT, RN, true,
439 bits(machInst, 5, 4), LSL, RM);
440 } else if (op1 == 6) {
441 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0);
442 } else if (op1 == 2 && op2Puw) {
443 %(str_puw)s;
444 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) {
445 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0);
446 } else if (op1 == 2 && op2 == 0) {
447 return new %(str_reg)s(machInst, RT, RN, true,
448 bits(machInst, 5, 4), LSL, RM);
449 } else {
450 return new Unknown(machInst);
451 }
452 }
453 '''
454 classNames = {
455 "strb_imm" : storeImmClassName(False, True, False, size=1),
456 "strb_puw" : buildPuwDecode(1),
457 "strbt" : storeImmClassName(False, True, False, user=True, size=1),
458 "strb_reg" : storeRegClassName(False, True, False, size=1),
459 "strh_imm" : storeImmClassName(False, True, False, size=2),
460 "strh_puw" : buildPuwDecode(2),
461 "strht" : storeImmClassName(False, True, False, user=True, size=2),
462 "strh_reg" : storeRegClassName(False, True, False, size=2),
463 "str_imm" : storeImmClassName(False, True, False),
464 "str_puw" : buildPuwDecode(4),
465 "strt" : storeImmClassName(False, True, False, user=True),
466 "str_reg" : storeRegClassName(False, True, False)
467 }
468 decode_block = decode % classNames
469}};
470
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Gabe Black
42
43def format AddrMode2(imm) {{
44 if eval(imm):
45 imm = True
46 else:
47 imm = False
48
49 def buildPUBWLCase(p, u, b, w, l):
50 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
51
52 header_output = decoder_output = exec_output = ""
53 decode_block = "switch(PUBWL) {\n"
54
55 # Loop over all the values of p, u, b, w and l and build instructions and
56 # a decode block for them.
57 for p in (0, 1):
58 for u in (0, 1):
59 for b in (0, 1):
60 for w in (0, 1):
61 post = (p == 0)
62 user = (p == 0 and w == 1)
63 writeback = (p == 0 or w == 1)
64 add = (u == 1)
65 if b == 0:
66 size = 4
67 else:
68 size = 1
69 if add:
70 addStr = "true"
71 else:
72 addStr = "false"
73 if imm:
74 newDecode = "return new %s(machInst, RD, RN," + \
75 "%s, machInst.immed11_0);"
76 loadClass = loadImmClassName(post, add, writeback,
77 size, False, user)
78 storeClass = storeImmClassName(post, add, writeback,
79 size, False, user)
80 loadDecode = newDecode % (loadClass, addStr)
81 storeDecode = newDecode % (storeClass, addStr)
82 else:
83 newDecode = "return new %s(machInst, RD, RN, %s," + \
84 "machInst.shiftSize," + \
85 "machInst.shift, RM);"
86 loadClass = loadRegClassName(post, add, writeback,
87 size, False, user)
88 storeClass = storeRegClassName(post, add, writeback,
89 size, False, user)
90 loadDecode = newDecode % (loadClass, addStr)
91 storeDecode = newDecode % (storeClass, addStr)
92 decode = '''
93 case %#x:
94 {%s}
95 break;
96 '''
97 decode_block += decode % \
98 (buildPUBWLCase(p,u,b,w,1), loadDecode)
99 decode_block += decode % \
100 (buildPUBWLCase(p,u,b,w,0), storeDecode)
101 decode_block += '''
102 default:
103 return new Unknown(machInst);
104 break;
105 }'''
106}};
107
108def format AddrMode3() {{
109 decode = '''
110 {
111 const uint32_t op1 = bits(machInst, 24, 20);
112 const uint32_t op2 = bits(machInst, 6, 5);
113 const uint32_t puiw = bits(machInst, 24, 21);
114 const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0;
115 switch (op2) {
116 case 0x1:
117 if (op1 & 0x1) {
118 %(ldrh)s
119 } else {
120 %(strh)s
121 }
122 case 0x2:
123 if (op1 & 0x1) {
124 %(ldrsb)s
125 } else {
126 %(ldrd)s
127 }
128 case 0x3:
129 if (op1 & 0x1) {
130 %(ldrsh)s
131 } else {
132 %(strd)s
133 }
134 default:
135 return new Unknown(machInst);
136 }
137 }
138 '''
139
140 def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False):
141 post = (p == 0)
142 user = (p == 0 and w == 1)
143 writeback = (p == 0 or w == 1)
144 add = (u == 1)
145 caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0)
146 decode = '''
147 case %#x:
148 return new '''% caseVal
149 if add:
150 addStr = "true"
151 else:
152 addStr = "false"
153 if i:
154 if load:
155 if d:
156 className = loadDoubleImmClassName(post, add, writeback)
157 else:
158 className = loadImmClassName(post, add, writeback, \
159 size=size, sign=sign, \
160 user=user)
161 else:
162 if d:
163 className = storeDoubleImmClassName(post, add, writeback)
164 else:
165 className = storeImmClassName(post, add, writeback, \
166 size=size, sign=sign, \
167 user=user)
168 decode += ("%s(machInst, RT, RN, %s, imm);\n" % \
169 (className, addStr))
170 else:
171 if load:
172 if d:
173 className = loadDoubleRegClassName(post, add, writeback)
174 else:
175 className = loadRegClassName(post, add, writeback, \
176 size=size, sign=sign, \
177 user=user)
178 else:
179 if d:
180 className = storeDoubleRegClassName(post, add, writeback)
181 else:
182 className = storeRegClassName(post, add, writeback, \
183 size=size, sign=sign, \
184 user=user)
185 decode += ("%s(machInst, RT, RN, %s, 0, LSL, RM);\n" % \
186 (className, addStr))
187 return decode
188
189 def decodePuiw(load, d, size=4, sign=False):
190 global decodePuiwCase
191 decode = "switch (puiw) {\n"
192 for p in (0, 1):
193 for u in (0, 1):
194 for i in (0, 1):
195 for w in (0, 1):
196 decode += decodePuiwCase(load, d, p, u, i, w,
197 size, sign)
198 decode += '''
199 default:
200 return new Unknown(machInst);
201 }
202 '''
203 return decode
204
205 subs = {
206 "ldrh" : decodePuiw(True, False, size=2),
207 "strh" : decodePuiw(False, False, size=2),
208 "ldrsb" : decodePuiw(True, False, size=1, sign=True),
209 "ldrd" : decodePuiw(True, True),
210 "ldrsh" : decodePuiw(True, False, size=2, sign=True),
211 "strd" : decodePuiw(False, True)
212 }
213 decode_block = decode % subs
214}};
215
216def format ArmSyncMem() {{
217 decode_block = '''
218 {
219 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
220 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
221 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
222 switch (PUBWL) {
223 case 0x10:
224 return new Swp(machInst, rt, rt2, rn);
225 case 0x14:
226 return new Swpb(machInst, rt, rt2, rn);
227 case 0x18:
228 return new WarnUnimplemented("strex", machInst);
229 case 0x19:
230 return new %(ldrex)s(machInst, rt, rn, true, 0);
231 case 0x1a:
232 return new WarnUnimplemented("strexd", machInst);
233 case 0x1b:
234 return new WarnUnimplemented("ldrexd", machInst);
235 case 0x1c:
236 return new WarnUnimplemented("strexb", machInst);
237 case 0x1d:
238 return new %(ldrexb)s(machInst, rt, rn, true, 0);
239 case 0x1e:
240 return new WarnUnimplemented("strexh", machInst);
241 case 0x1f:
242 return new %(ldrexh)s(machInst, rt, rn, true, 0);
243 default:
244 return new Unknown(machInst);
245 }
246 }
247 ''' % {
248 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
249 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
250 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2)
251 }
252}};
253
254def format Thumb32LdrStrDExTbh() {{
255 decode_block = '''
256 {
257 const uint32_t op1 = bits(machInst, 24, 23);
258 const uint32_t op2 = bits(machInst, 21, 20);
259 const uint32_t op3 = bits(machInst, 7, 4);
260 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
261 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
262 /* This isn't used yet, and that makes gcc upset. */
263 //const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
264 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
265 if (op1 == 0) {
266 const uint32_t imm = bits(machInst, 7, 0) << 2;
267 if (op2 == 0) {
268 return new WarnUnimplemented("strex", machInst);
269 } else {
270 return new %(ldrex)s(machInst, rt, rn, true, imm);
271 }
272 } else {
273 if (op2 == 0) {
274 switch (op3) {
275 case 0x4:
276 return new WarnUnimplemented("strexb", machInst);
277 case 0x5:
278 return new WarnUnimplemented("strexh", machInst);
279 case 0x7:
280 return new WarnUnimplemented("strexd", machInst);
281 default:
282 return new Unknown(machInst);
283 }
284 } else {
285 switch (op3) {
286 case 0x0:
287 return new WarnUnimplemented("tbb", machInst);
288 case 0x1:
289 return new WarnUnimplemented("tbh", machInst);
290 case 0x4:
291 return new %(ldrexb)s(machInst, rt, rn, true, 0);
292 case 0x5:
293 return new %(ldrexh)s(machInst, rt, rn, true, 0);
294 case 0x7:
295 return new WarnUnimplemented("ldrexd", machInst);
296 default:
297 return new Unknown(machInst);
298 }
299 }
300 }
301 } else {
302 if (bits(op2, 0) == 0) {
303 return new WarnUnimplemented("strd", machInst);
304 } else {
305 return new WarnUnimplemented("ldrd", machInst);
306 }
307 }
308 }
309 ''' % {
310 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
311 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
312 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2)
313 }
314}};
315
316def format Thumb32LoadWord() {{
317 decode = '''
318 {
319 uint32_t op1 = bits(machInst, 24, 23);
320 if (bits(op1, 1) == 0) {
321 uint32_t op2 = bits(machInst, 11, 6);
322 if (HTRN == 0xF) {
323 if (UP) {
324 return new %(literal_u)s(machInst, RT, INTREG_PC,
325 true, IMMED_11_0);
326 } else {
327 return new %(literal)s(machInst, RT, INTREG_PC,
328 false, IMMED_11_0);
329 }
330 } else if (op1 == 0x1) {
331 return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0);
332 } else if (op2 == 0) {
333 return new %(register)s(machInst, RT, RN, UP,
334 bits(machInst, 5, 4), LSL, RM);
335 } else if ((op2 & 0x3c) == 0x38) {
336 return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0);
337 } else if ((op2 & 0x3c) == 0x30 || //P
338 (op2 & 0x24) == 0x24) { //W
339 uint32_t puw = bits(machInst, 10, 8);
340 uint32_t imm = IMMED_7_0;
341 switch (puw) {
342 case 0:
343 case 2:
344 // If we're here, either P or W must have been set.
345 panic("Neither P or W set, but that "
346 "shouldn't be possible.\\n");
347 case 1:
348 return new %(imm_w)s(machInst, RT, RN, false, imm);
349 case 3:
350 return new %(imm_uw)s(machInst, RT, RN, true, imm);
351 case 4:
352 return new %(imm_p)s(machInst, RT, RN, false, imm);
353 case 5:
354 return new %(imm_pw)s(machInst, RT, RN, false, imm);
355 case 6:
356 return new %(imm_pu)s(machInst, RT, RN, true, imm);
357 case 7:
358 return new %(imm_puw)s(machInst, RT, RN, true, imm);
359 }
360 }
361 } else {
362 return new Unknown(machInst);
363 }
364 }
365 '''
366 classNames = {
367 "literal_u" : loadImmClassName(False, True, False),
368 "literal" : loadImmClassName(False, False, False),
369 "register" : loadRegClassName(False, True, False),
370 "ldrt" : loadImmClassName(False, True, False, user=True),
371 "imm_w" : loadImmClassName(True, False, True),
372 "imm_uw" : loadImmClassName(True, True, True),
373 "imm_p" : loadImmClassName(False, False, False),
374 "imm_pw" : loadImmClassName(False, False, True),
375 "imm_pu" : loadImmClassName(False, True, False),
376 "imm_puw" : loadImmClassName(False, True, True)
377 }
378 decode_block = decode % classNames
379}};
380
381def format Thumb32StoreSingle() {{
382 def buildPuwDecode(size):
383 puwDecode = '''
384 {
385 uint32_t puw = bits(machInst, 10, 8);
386 uint32_t imm = IMMED_7_0;
387 switch (puw) {
388 case 0:
389 case 2:
390 // If we're here, either P or W must have been set.
391 panic("Neither P or W set, but that "
392 "shouldn't be possible.\\n");
393 case 1:
394 return new %(imm_w)s(machInst, RT, RN, false, imm);
395 case 3:
396 return new %(imm_uw)s(machInst, RT, RN, true, imm);
397 case 4:
398 return new %(imm_p)s(machInst, RT, RN, false, imm);
399 case 5:
400 return new %(imm_pw)s(machInst, RT, RN, false, imm);
401 case 6:
402 return new %(imm_pu)s(machInst, RT, RN, true, imm);
403 case 7:
404 return new %(imm_puw)s(machInst, RT, RN, true, imm);
405 }
406 }
407 '''
408 return puwDecode % {
409 "imm_w" : storeImmClassName(True, False, True, size=size),
410 "imm_uw" : storeImmClassName(True, True, True, size=size),
411 "imm_p" : storeImmClassName(False, False, False, size=size),
412 "imm_pw" : storeImmClassName(False, False, True, size=size),
413 "imm_pu" : storeImmClassName(False, True, False, size=size),
414 "imm_puw" : storeImmClassName(False, True, True, size=size)
415 }
416 decode = '''
417 {
418 uint32_t op1 = bits(machInst, 23, 21);
419 uint32_t op2 = bits(machInst, 11, 6);
420 bool op2Puw = ((op2 & 0x24) == 0x24 ||
421 (op2 & 0x3c) == 0x30);
422 if (op1 == 4) {
423 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0);
424 } else if (op1 == 0 && op2Puw) {
425 %(strb_puw)s;
426 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) {
427 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0);
428 } else if (op1 == 0 && op2 == 0) {
429 return new %(strb_reg)s(machInst, RT, RN, true,
430 bits(machInst, 5, 4), LSL, RM);
431 } else if (op1 == 5) {
432 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0);
433 } else if (op1 == 1 && op2Puw) {
434 %(strh_puw)s;
435 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) {
436 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0);
437 } else if (op1 == 1 && op2 == 0) {
438 return new %(strh_reg)s(machInst, RT, RN, true,
439 bits(machInst, 5, 4), LSL, RM);
440 } else if (op1 == 6) {
441 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0);
442 } else if (op1 == 2 && op2Puw) {
443 %(str_puw)s;
444 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) {
445 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0);
446 } else if (op1 == 2 && op2 == 0) {
447 return new %(str_reg)s(machInst, RT, RN, true,
448 bits(machInst, 5, 4), LSL, RM);
449 } else {
450 return new Unknown(machInst);
451 }
452 }
453 '''
454 classNames = {
455 "strb_imm" : storeImmClassName(False, True, False, size=1),
456 "strb_puw" : buildPuwDecode(1),
457 "strbt" : storeImmClassName(False, True, False, user=True, size=1),
458 "strb_reg" : storeRegClassName(False, True, False, size=1),
459 "strh_imm" : storeImmClassName(False, True, False, size=2),
460 "strh_puw" : buildPuwDecode(2),
461 "strht" : storeImmClassName(False, True, False, user=True, size=2),
462 "strh_reg" : storeRegClassName(False, True, False, size=2),
463 "str_imm" : storeImmClassName(False, True, False),
464 "str_puw" : buildPuwDecode(4),
465 "strt" : storeImmClassName(False, True, False, user=True),
466 "str_reg" : storeRegClassName(False, True, False)
467 }
468 decode_block = decode % classNames
469}};
470
|
| 471def format LoadByteMemoryHints() {{
472 decode = '''
473 {
474 const uint32_t op1 = bits(machInst, 24, 23);
475 const uint32_t op2 = bits(machInst, 11, 6);
476 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
477 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
478 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
479 const uint32_t imm12 = bits(machInst, 11, 0);
480 const uint32_t imm8 = bits(machInst, 7, 0);
481 bool pldw = bits(machInst, 21);
482 const uint32_t imm2 = bits(machInst, 5, 4);
483 if (rn == 0xf) {
484 if (rt == 0xf) {
485 const bool add = bits(machInst, 23);
486 if (bits(op1, 1) == 1) {
487 if (add) {
488 return new %(pli_iulit)s(machInst, INTREG_ZERO,
489 INTREG_PC, true, imm12);
490 } else {
491 return new %(pli_ilit)s(machInst, INTREG_ZERO,
492 INTREG_PC, false, imm12);
493 }
494 } else {
495 if (add) {
496 return new %(pld_iulit)s(machInst, INTREG_ZERO,
497 INTREG_PC, true, imm12);
498 } else {
499 return new %(pld_ilit)s(machInst, INTREG_ZERO,
500 INTREG_PC, false, imm12);
501 }
502 }
503 } else {
504 if (bits(op1, 1) == 1) {
505 if (bits(machInst, 23)) {
506 return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC,
507 true, imm12);
508 } else {
509 return new %(ldrsb_lit)s(machInst, rt, INTREG_PC,
510 false, imm12);
511 }
512 } else {
513 if (bits(machInst, 23)) {
514 return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC,
515 true, imm12);
516 } else {
517 return new %(ldrb_lit)s(machInst, rt, INTREG_PC,
518 false, imm12);
519 }
520 }
521 }
522 } else if (rt == 0xf) {
523 switch (op1) {
524 case 0x0:
525 if (op2 == 0x0) {
526 if (pldw) {
527 return new %(pldw_radd)s(machInst, INTREG_ZERO,
528 rn, true, imm2, LSL, rm);
529 } else {
530 return new %(pld_radd)s(machInst, INTREG_ZERO,
531 rn, true, imm2, LSL, rm);
532 }
533 } else if (bits(op2, 5, 2) == 0xc) {
534 if (pldw) {
535 return new %(pldw_isub)s(machInst, INTREG_ZERO,
536 rn, false, imm8);
537 } else {
538 return new %(pld_isub)s(machInst, INTREG_ZERO,
539 rn, false, imm8);
540 }
541 }
542 break;
543 case 0x1:
544 if (pldw) {
545 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
546 rn, true, imm12);
547 } else {
548 return new %(pld_iadd)s(machInst, INTREG_ZERO,
549 rn, true, imm12);
550 }
551 case 0x2:
552 if (op2 == 0x0) {
553 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
554 true, imm2, LSL, rm);
555 } else if (bits(op2, 5, 2) == 0xc) {
556 return new %(pli_ilit)s(machInst, INTREG_ZERO,
557 INTREG_PC, false, imm8);
558 }
559 break;
560 case 0x3:
561 return new %(pli_iulit)s(machInst, INTREG_ZERO,
562 INTREG_PC, true, imm12);
563 }
564 return new Unknown(machInst);
565 } else {
566 switch (op1) {
567 case 0x0:
568 if (op2 == 0) {
569 return new %(ldrb_radd)s(machInst, rt, rn, true,
570 imm2, LSL, rm);
571 } else if (bits(op2, 5, 2) == 0xe) {
572 return new %(ldrbt)s(machInst, rt, rn, true, imm8);
573 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
574 const uint32_t puw = bits(machInst, 10, 8);
575 switch (puw) {
576 case 0x1:
577 return new %(ldrb_iw)s(machInst, rt,
578 rn, false, imm8);
579 case 0x3:
580 return new %(ldrb_iuw)s(machInst, rt,
581 rn, true, imm8);
582 case 0x4:
583 return new %(ldrb_ip)s(machInst, rt,
584 rn, false, imm8);
585 case 0x5:
586 return new %(ldrb_ipw)s(machInst, rt,
587 rn, false, imm8);
588 case 0x7:
589 return new %(ldrb_ipuw)s(machInst, rt,
590 rn, true, imm8);
591 }
592 }
593 break;
594 case 0x1:
595 return new %(ldrb_iadd)s(machInst, rt, rn, true, imm12);
596 case 0x2:
597 if (op2 == 0) {
598 return new %(ldrsb_radd)s(machInst, rt, rn, true,
599 imm2, LSL, rm);
600 } else if (bits(op2, 5, 2) == 0xe) {
601 return new %(ldrsbt)s(machInst, rt, rn, true, imm8);
602 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
603 const uint32_t puw = bits(machInst, 10, 8);
604 switch (puw) {
605 case 0x1:
606 return new %(ldrsb_iw)s(machInst, rt,
607 rn, false, imm8);
608 case 0x3:
609 return new %(ldrsb_iuw)s(machInst, rt,
610 rn, true, imm8);
611 case 0x4:
612 return new %(ldrsb_ip)s(machInst, rt,
613 rn, false, imm8);
614 case 0x5:
615 return new %(ldrsb_ipw)s(machInst, rt,
616 rn, false, imm8);
617 case 0x7:
618 return new %(ldrsb_ipuw)s(machInst, rt,
619 rn, true, imm8);
620 }
621 }
622 break;
623 case 0x3:
624 return new %(ldrsb_iadd)s(machInst, rt, rn, true, imm12);
625 }
626 return new Unknown(machInst);
627 }
628 }
629 '''
630 substDict = {
631 "ldrsb_lit_u" : loadImmClassName(False, True, False, 1, True),
632 "ldrsb_lit" : loadImmClassName(False, False, False, 1, True),
633 "ldrb_lit_u" : loadImmClassName(False, True, False, 1),
634 "ldrb_lit" : loadImmClassName(False, False, False, 1),
635 "ldrsb_radd" : loadRegClassName(False, True, False, 1, True),
636 "ldrb_radd" : loadRegClassName(False, True, False, 1),
637 "ldrsb_iw" : loadImmClassName(True, False, True, 1, True),
638 "ldrsb_iuw" : loadImmClassName(True, True, True, 1, True),
639 "ldrsb_ip" : loadImmClassName(False, False, False, 1, True),
640 "ldrsb_ipw" : loadImmClassName(False, False, True, 1, True),
641 "ldrsb_ipuw" : loadImmClassName(False, True, True, 1, True),
642 "ldrsb_iadd" : loadImmClassName(False, True, False, 1, True),
643 "ldrb_iw" : loadImmClassName(True, False, True, 1),
644 "ldrb_iuw" : loadImmClassName(True, True, True, 1),
645 "ldrb_ip" : loadImmClassName(False, False, False, 1),
646 "ldrb_ipw" : loadImmClassName(False, False, True, 1),
647 "ldrb_ipuw" : loadImmClassName(False, True, True, 1),
648 "ldrb_iadd" : loadImmClassName(False, True, False, 1),
649 "ldrbt" : loadImmClassName(False, True, False, 1, user=True),
650 "ldrsbt" : loadImmClassName(False, True, False, 1, True, user=True),
651 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
652 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
653 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
654 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
655 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
656 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
657 "pld_iulit" : "PLD_" + loadImmClassName(False, True, False, 1),
658 "pld_ilit" : "PLD_" + loadImmClassName(False, False, False, 1),
659 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1),
660 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1),
661 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
662 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1),
663 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1)
664 }
665 decode_block = decode % substDict
666}};
667
|
471def format LoadHalfwordMemoryHints() {{
472 decode = '''
473 {
474 const uint32_t op1 = bits(machInst, 24, 23);
475 const uint32_t op2 = bits(machInst, 11, 6);
476 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
477 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
478 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
479 const uint32_t imm12 = bits(machInst, 11, 0);
480 const uint32_t imm8 = bits(machInst, 7, 0);
481 bool pldw = bits(machInst, 21);
482 const uint32_t imm2 = bits(machInst, 5, 4);
483 if (rn == 0xf) {
484 if (rt == 0xf) {
485 if (bits(op1, 1) == 1) {
486 // Unallocated memory hint
487 return new NopInst(machInst);
488 } else {
489 return new Unknown(machInst);
490 }
491 } else {
492 if (bits(op1, 1) == 1) {
493 if (bits(machInst, 23)) {
494 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC,
495 true, imm12);
496 } else {
497 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC,
498 false, imm12);
499 }
500 } else {
501 if (bits(machInst, 23)) {
502 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC,
503 true, imm12);
504 } else {
505 return new %(ldrh_lit)s(machInst, rt, INTREG_PC,
506 false, imm12);
507 }
508 }
509 }
510 } else if (rt == 0xf) {
511 switch (op1) {
512 case 0x0:
513 if (op2 == 0x0) {
514 if (pldw) {
515 return new %(pldw_radd)s(machInst, INTREG_ZERO,
516 rn, true, imm2, LSL, rm);
517 } else {
518 return new %(pld_radd)s(machInst, INTREG_ZERO,
519 rn, true, imm2, LSL, rm);
520 }
521 } else if (bits(op2, 5, 2) == 0xc) {
522 if (pldw) {
523 return new %(pldw_isub)s(machInst, INTREG_ZERO,
524 rn, false, imm8);
525 } else {
526 return new %(pld_isub)s(machInst, INTREG_ZERO,
527 rn, false, imm8);
528 }
529 }
530 break;
531 case 0x1:
532 if (pldw) {
533 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
534 rn, true, imm12);
535 } else {
536 return new %(pld_iadd)s(machInst, INTREG_ZERO,
537 rn, true, imm12);
538 }
539 case 0x2:
540 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) {
541 // Unallocated memory hint
542 return new NopInst(machInst);
543 }
544 break;
545 case 0x3:
546 return new NopInst(machInst);
547 }
548 return new Unknown(machInst);
549 } else {
550 switch (op1) {
551 case 0x0:
552 if (op2 == 0) {
553 return new %(ldrh_radd)s(machInst, rt, rn, true,
554 imm2, LSL, rm);
555 } else if (bits(op2, 5, 2) == 0xe) {
556 return new %(ldrht)s(machInst, rt, rn, true, imm8);
557 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
558 const uint32_t puw = bits(machInst, 10, 8);
559 switch (puw) {
560 case 0x1:
561 return new %(ldrh_iw)s(machInst, rt,
562 rn, false, imm8);
563 case 0x3:
564 return new %(ldrh_iuw)s(machInst, rt,
565 rn, true, imm8);
566 case 0x4:
567 return new %(ldrh_ip)s(machInst, rt,
568 rn, false, imm8);
569 case 0x5:
570 return new %(ldrh_ipw)s(machInst, rt,
571 rn, false, imm8);
572 case 0x7:
573 return new %(ldrh_ipuw)s(machInst, rt,
574 rn, true, imm8);
575 }
576 }
577 break;
578 case 0x1:
579 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12);
580 case 0x2:
581 if (op2 == 0) {
582 return new %(ldrsh_radd)s(machInst, rt, rn, true,
583 imm2, LSL, rm);
584 } else if (bits(op2, 5, 2) == 0xe) {
585 return new %(ldrsht)s(machInst, rt, rn, true, imm8);
586 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
587 const uint32_t puw = bits(machInst, 10, 8);
588 switch (puw) {
589 case 0x1:
590 return new %(ldrsh_iw)s(machInst, rt,
591 rn, false, imm8);
592 case 0x3:
593 return new %(ldrsh_iuw)s(machInst, rt,
594 rn, true, imm8);
595 case 0x4:
596 return new %(ldrsh_ip)s(machInst, rt,
597 rn, false, imm8);
598 case 0x5:
599 return new %(ldrsh_ipw)s(machInst, rt,
600 rn, false, imm8);
601 case 0x7:
602 return new %(ldrsh_ipuw)s(machInst, rt,
603 rn, true, imm8);
604 }
605 }
606 break;
607 case 0x3:
608 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12);
609 }
610 return new Unknown(machInst);
611 }
612 }
613 '''
614 substDict = {
615 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True),
616 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True),
617 "ldrh_lit_u" : loadImmClassName(False, True, False, 2),
618 "ldrh_lit" : loadImmClassName(False, False, False, 2),
619 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True),
620 "ldrh_radd" : loadRegClassName(False, True, False, 2),
621 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True),
622 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True),
623 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True),
624 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True),
625 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True),
626 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True),
627 "ldrh_iw" : loadImmClassName(True, False, True, 2),
628 "ldrh_iuw" : loadImmClassName(True, True, True, 2),
629 "ldrh_ip" : loadImmClassName(False, False, False, 2),
630 "ldrh_ipw" : loadImmClassName(False, False, True, 2),
631 "ldrh_ipuw" : loadImmClassName(False, True, True, 2),
632 "ldrh_iadd" : loadImmClassName(False, True, False, 2),
633 "ldrht" : loadImmClassName(False, True, False, 2, user=True),
634 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True),
635 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
636 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
637 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
638 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
639 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
640 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1)
641 }
642 decode_block = decode % substDict
643}};
644
645def format Thumb16MemReg() {{
646 decode = '''
647 {
648 const uint32_t opb = bits(machInst, 11, 9);
649 const uint32_t rt = bits(machInst, 2, 0);
650 const uint32_t rn = bits(machInst, 5, 3);
651 const uint32_t rm = bits(machInst, 8, 6);
652 switch (opb) {
653 case 0x0:
654 return new %(str)s(machInst, rt, rn, true, 0, LSL, rm);
655 case 0x1:
656 return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm);
657 case 0x2:
658 return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm);
659 case 0x3:
660 return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm);
661 case 0x4:
662 return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm);
663 case 0x5:
664 return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm);
665 case 0x6:
666 return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm);
667 case 0x7:
668 return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm);
669 }
670 }
671 '''
672 classNames = {
673 "str" : storeRegClassName(False, True, False),
674 "strh" : storeRegClassName(False, True, False, size=2),
675 "strb" : storeRegClassName(False, True, False, size=1),
676 "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1),
677 "ldr" : loadRegClassName(False, True, False),
678 "ldrh" : loadRegClassName(False, True, False, size=2),
679 "ldrb" : loadRegClassName(False, True, False, size=1),
680 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2),
681 }
682 decode_block = decode % classNames
683}};
684
685def format Thumb16MemImm() {{
686 decode = '''
687 {
688 const uint32_t opa = bits(machInst, 15, 12);
689 const uint32_t opb = bits(machInst, 11, 9);
690 const uint32_t lrt = bits(machInst, 2, 0);
691 const uint32_t lrn = bits(machInst, 5, 3);
692 const uint32_t hrt = bits(machInst, 10, 8);
693 const uint32_t imm5 = bits(machInst, 10, 6);
694 const uint32_t imm8 = bits(machInst, 7, 0);
695 const bool load = bits(opb, 2);
696 switch (opa) {
697 case 0x6:
698 if (load) {
699 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2);
700 } else {
701 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2);
702 }
703 case 0x7:
704 if (load) {
705 return new %(ldrb)s(machInst, lrt, lrn, true, imm5);
706 } else {
707 return new %(strb)s(machInst, lrt, lrn, true, imm5);
708 }
709 case 0x8:
710 if (load) {
711 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1);
712 } else {
713 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1);
714 }
715 case 0x9:
716 if (load) {
717 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
718 } else {
719 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
720 }
721 default:
722 return new Unknown(machInst);
723 }
724 }
725 '''
726 classNames = {
727 "ldr" : loadImmClassName(False, True, False),
728 "str" : storeImmClassName(False, True, False),
729 "ldrh" : loadImmClassName(False, True, False, size=2),
730 "strh" : storeImmClassName(False, True, False, size=2),
731 "ldrb" : loadImmClassName(False, True, False, size=1),
732 "strb" : storeImmClassName(False, True, False, size=1),
733 }
734 decode_block = decode % classNames
735}};
736
737def format Thumb16MemLit() {{
738 decode_block = '''
739 {
740 const uint32_t rt = bits(machInst, 10, 8);
741 const uint32_t imm8 = bits(machInst, 7, 0);
742 return new %s(machInst, rt, INTREG_PC, true, imm8 << 2);
743 }
744 ''' % loadImmClassName(False, True, False)
745}};
746
| 668def format LoadHalfwordMemoryHints() {{
669 decode = '''
670 {
671 const uint32_t op1 = bits(machInst, 24, 23);
672 const uint32_t op2 = bits(machInst, 11, 6);
673 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
674 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
675 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
676 const uint32_t imm12 = bits(machInst, 11, 0);
677 const uint32_t imm8 = bits(machInst, 7, 0);
678 bool pldw = bits(machInst, 21);
679 const uint32_t imm2 = bits(machInst, 5, 4);
680 if (rn == 0xf) {
681 if (rt == 0xf) {
682 if (bits(op1, 1) == 1) {
683 // Unallocated memory hint
684 return new NopInst(machInst);
685 } else {
686 return new Unknown(machInst);
687 }
688 } else {
689 if (bits(op1, 1) == 1) {
690 if (bits(machInst, 23)) {
691 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC,
692 true, imm12);
693 } else {
694 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC,
695 false, imm12);
696 }
697 } else {
698 if (bits(machInst, 23)) {
699 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC,
700 true, imm12);
701 } else {
702 return new %(ldrh_lit)s(machInst, rt, INTREG_PC,
703 false, imm12);
704 }
705 }
706 }
707 } else if (rt == 0xf) {
708 switch (op1) {
709 case 0x0:
710 if (op2 == 0x0) {
711 if (pldw) {
712 return new %(pldw_radd)s(machInst, INTREG_ZERO,
713 rn, true, imm2, LSL, rm);
714 } else {
715 return new %(pld_radd)s(machInst, INTREG_ZERO,
716 rn, true, imm2, LSL, rm);
717 }
718 } else if (bits(op2, 5, 2) == 0xc) {
719 if (pldw) {
720 return new %(pldw_isub)s(machInst, INTREG_ZERO,
721 rn, false, imm8);
722 } else {
723 return new %(pld_isub)s(machInst, INTREG_ZERO,
724 rn, false, imm8);
725 }
726 }
727 break;
728 case 0x1:
729 if (pldw) {
730 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
731 rn, true, imm12);
732 } else {
733 return new %(pld_iadd)s(machInst, INTREG_ZERO,
734 rn, true, imm12);
735 }
736 case 0x2:
737 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) {
738 // Unallocated memory hint
739 return new NopInst(machInst);
740 }
741 break;
742 case 0x3:
743 return new NopInst(machInst);
744 }
745 return new Unknown(machInst);
746 } else {
747 switch (op1) {
748 case 0x0:
749 if (op2 == 0) {
750 return new %(ldrh_radd)s(machInst, rt, rn, true,
751 imm2, LSL, rm);
752 } else if (bits(op2, 5, 2) == 0xe) {
753 return new %(ldrht)s(machInst, rt, rn, true, imm8);
754 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
755 const uint32_t puw = bits(machInst, 10, 8);
756 switch (puw) {
757 case 0x1:
758 return new %(ldrh_iw)s(machInst, rt,
759 rn, false, imm8);
760 case 0x3:
761 return new %(ldrh_iuw)s(machInst, rt,
762 rn, true, imm8);
763 case 0x4:
764 return new %(ldrh_ip)s(machInst, rt,
765 rn, false, imm8);
766 case 0x5:
767 return new %(ldrh_ipw)s(machInst, rt,
768 rn, false, imm8);
769 case 0x7:
770 return new %(ldrh_ipuw)s(machInst, rt,
771 rn, true, imm8);
772 }
773 }
774 break;
775 case 0x1:
776 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12);
777 case 0x2:
778 if (op2 == 0) {
779 return new %(ldrsh_radd)s(machInst, rt, rn, true,
780 imm2, LSL, rm);
781 } else if (bits(op2, 5, 2) == 0xe) {
782 return new %(ldrsht)s(machInst, rt, rn, true, imm8);
783 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
784 const uint32_t puw = bits(machInst, 10, 8);
785 switch (puw) {
786 case 0x1:
787 return new %(ldrsh_iw)s(machInst, rt,
788 rn, false, imm8);
789 case 0x3:
790 return new %(ldrsh_iuw)s(machInst, rt,
791 rn, true, imm8);
792 case 0x4:
793 return new %(ldrsh_ip)s(machInst, rt,
794 rn, false, imm8);
795 case 0x5:
796 return new %(ldrsh_ipw)s(machInst, rt,
797 rn, false, imm8);
798 case 0x7:
799 return new %(ldrsh_ipuw)s(machInst, rt,
800 rn, true, imm8);
801 }
802 }
803 break;
804 case 0x3:
805 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12);
806 }
807 return new Unknown(machInst);
808 }
809 }
810 '''
811 substDict = {
812 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True),
813 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True),
814 "ldrh_lit_u" : loadImmClassName(False, True, False, 2),
815 "ldrh_lit" : loadImmClassName(False, False, False, 2),
816 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True),
817 "ldrh_radd" : loadRegClassName(False, True, False, 2),
818 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True),
819 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True),
820 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True),
821 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True),
822 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True),
823 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True),
824 "ldrh_iw" : loadImmClassName(True, False, True, 2),
825 "ldrh_iuw" : loadImmClassName(True, True, True, 2),
826 "ldrh_ip" : loadImmClassName(False, False, False, 2),
827 "ldrh_ipw" : loadImmClassName(False, False, True, 2),
828 "ldrh_ipuw" : loadImmClassName(False, True, True, 2),
829 "ldrh_iadd" : loadImmClassName(False, True, False, 2),
830 "ldrht" : loadImmClassName(False, True, False, 2, user=True),
831 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True),
832 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
833 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
834 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
835 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
836 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
837 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1)
838 }
839 decode_block = decode % substDict
840}};
841
842def format Thumb16MemReg() {{
843 decode = '''
844 {
845 const uint32_t opb = bits(machInst, 11, 9);
846 const uint32_t rt = bits(machInst, 2, 0);
847 const uint32_t rn = bits(machInst, 5, 3);
848 const uint32_t rm = bits(machInst, 8, 6);
849 switch (opb) {
850 case 0x0:
851 return new %(str)s(machInst, rt, rn, true, 0, LSL, rm);
852 case 0x1:
853 return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm);
854 case 0x2:
855 return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm);
856 case 0x3:
857 return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm);
858 case 0x4:
859 return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm);
860 case 0x5:
861 return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm);
862 case 0x6:
863 return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm);
864 case 0x7:
865 return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm);
866 }
867 }
868 '''
869 classNames = {
870 "str" : storeRegClassName(False, True, False),
871 "strh" : storeRegClassName(False, True, False, size=2),
872 "strb" : storeRegClassName(False, True, False, size=1),
873 "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1),
874 "ldr" : loadRegClassName(False, True, False),
875 "ldrh" : loadRegClassName(False, True, False, size=2),
876 "ldrb" : loadRegClassName(False, True, False, size=1),
877 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2),
878 }
879 decode_block = decode % classNames
880}};
881
882def format Thumb16MemImm() {{
883 decode = '''
884 {
885 const uint32_t opa = bits(machInst, 15, 12);
886 const uint32_t opb = bits(machInst, 11, 9);
887 const uint32_t lrt = bits(machInst, 2, 0);
888 const uint32_t lrn = bits(machInst, 5, 3);
889 const uint32_t hrt = bits(machInst, 10, 8);
890 const uint32_t imm5 = bits(machInst, 10, 6);
891 const uint32_t imm8 = bits(machInst, 7, 0);
892 const bool load = bits(opb, 2);
893 switch (opa) {
894 case 0x6:
895 if (load) {
896 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2);
897 } else {
898 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2);
899 }
900 case 0x7:
901 if (load) {
902 return new %(ldrb)s(machInst, lrt, lrn, true, imm5);
903 } else {
904 return new %(strb)s(machInst, lrt, lrn, true, imm5);
905 }
906 case 0x8:
907 if (load) {
908 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1);
909 } else {
910 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1);
911 }
912 case 0x9:
913 if (load) {
914 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
915 } else {
916 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
917 }
918 default:
919 return new Unknown(machInst);
920 }
921 }
922 '''
923 classNames = {
924 "ldr" : loadImmClassName(False, True, False),
925 "str" : storeImmClassName(False, True, False),
926 "ldrh" : loadImmClassName(False, True, False, size=2),
927 "strh" : storeImmClassName(False, True, False, size=2),
928 "ldrb" : loadImmClassName(False, True, False, size=1),
929 "strb" : storeImmClassName(False, True, False, size=1),
930 }
931 decode_block = decode % classNames
932}};
933
934def format Thumb16MemLit() {{
935 decode_block = '''
936 {
937 const uint32_t rt = bits(machInst, 10, 8);
938 const uint32_t imm8 = bits(machInst, 7, 0);
939 return new %s(machInst, rt, INTREG_PC, true, imm8 << 2);
940 }
941 ''' % loadImmClassName(False, True, False)
942}};
943
|