mem.isa (7045:e21fe6a62b1c) | mem.isa (7119:5ad962dec52f) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// |
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3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright --- 56 unchanged lines hidden (view full) --- 67 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 69 { 70 %(constructor)s; 71 } 72}}; 73 74 | 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright --- 56 unchanged lines hidden (view full) --- 79 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 80 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 81 { 82 %(constructor)s; 83 } 84}}; 85 86 |
75def template LoadExecute {{ 76 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 77 Trace::InstRecord *traceData) const 78 { 79 Addr EA; 80 Fault fault = NoFault; 81 82 %(op_decl)s; 83 %(op_rd)s; 84 %(ea_code)s; 85 86 if (%(predicate_test)s) 87 { 88 if (fault == NoFault) { 89 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 90 %(memacc_code)s; 91 } 92 93 if (fault == NoFault) { 94 %(op_wb)s; 95 } 96 } 97 98 return fault; 99 } 100}}; 101 102 103def template LoadInitiateAcc {{ 104 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 105 Trace::InstRecord *traceData) const 106 { 107 Addr EA; 108 Fault fault = NoFault; 109 110 %(op_src_decl)s; 111 %(op_rd)s; 112 %(ea_code)s; 113 114 if (%(predicate_test)s) 115 { 116 if (fault == NoFault) { 117 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 118 } 119 } 120 121 return fault; 122 } 123}}; 124 125 126def template LoadCompleteAcc {{ 127 Fault %(class_name)s::completeAcc(PacketPtr pkt, 128 %(CPU_exec_context)s *xc, 129 Trace::InstRecord *traceData) const 130 { 131 Fault fault = NoFault; 132 133 %(op_decl)s; 134 %(op_rd)s; 135 136 if (%(predicate_test)s) 137 { 138 // ARM instructions will not have a pkt if the predicate is false 139 Mem = pkt->get<typeof(Mem)>(); 140 141 if (fault == NoFault) { 142 %(memacc_code)s; 143 } 144 145 if (fault == NoFault) { 146 %(op_wb)s; 147 } 148 } 149 150 return fault; 151 } 152}}; 153 154 | |
155def template StoreExecute {{ 156 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 157 Trace::InstRecord *traceData) const 158 { 159 Addr EA; 160 Fault fault = NoFault; 161 162 %(op_decl)s; --- 128 unchanged lines hidden (view full) --- 291 newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w) 292 suffix = ("Reg", "Hilo")[i] 293 return LoadStoreBase(mnem, mnem.capitalize() + newSuffix, 294 ea_code, code, mem_flags = [], inst_flags = [], 295 base_class = 'Memory' + suffix, 296 exec_template_base = type.capitalize()) 297}}; 298 | 87def template StoreExecute {{ 88 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 89 Trace::InstRecord *traceData) const 90 { 91 Addr EA; 92 Fault fault = NoFault; 93 94 %(op_decl)s; --- 128 unchanged lines hidden (view full) --- 223 newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w) 224 suffix = ("Reg", "Hilo")[i] 225 return LoadStoreBase(mnem, mnem.capitalize() + newSuffix, 226 ea_code, code, mem_flags = [], inst_flags = [], 227 base_class = 'Memory' + suffix, 228 exec_template_base = type.capitalize()) 229}}; 230 |
299def format AddrMode2(suffix, offset) {{ | 231def format AddrMode2(imm, suffix, offset) {{ 232 if eval(imm): 233 imm = True 234 else: 235 imm = False 236 |
300 header_output = decoder_output = exec_output = "" 301 decode_block = "switch(PUBWL) {\n" 302 303 # Loop over all the values of p, u, b, w and l and build instructions and 304 # a decode block for them. 305 for p in (0, 1): 306 for u in (0, 1): 307 for b in (0, 1): 308 for w in (0, 1): | 237 header_output = decoder_output = exec_output = "" 238 decode_block = "switch(PUBWL) {\n" 239 240 # Loop over all the values of p, u, b, w and l and build instructions and 241 # a decode block for them. 242 for p in (0, 1): 243 for u in (0, 1): 244 for b in (0, 1): 245 for w in (0, 1): |
309 for l in (0, 1): 310 (new_header_output, 311 new_decoder_output, 312 new_decode_block, 313 new_exec_output) = buildMode2Inst(p, u, b, w, l, 314 suffix, offset) 315 header_output += new_header_output 316 decoder_output += new_decoder_output 317 exec_output += new_exec_output 318 decode_block += ''' 319 case %#x: 320 {%s} 321 break; 322 ''' % (buildPUBWLCase(p,u,b,w,l), new_decode_block) | 246 (new_header_output, 247 new_decoder_output, 248 new_decode_block, 249 new_exec_output) = buildMode2Inst(p, u, b, w, 0, 250 suffix, offset) 251 header_output += new_header_output 252 decoder_output += new_decoder_output 253 exec_output += new_exec_output 254 decode_block += ''' 255 case %#x: 256 {%s} 257 break; 258 ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block) 259 260 post = (p == 0) 261 user = (p == 0 and w == 0) 262 writeback = (p == 0 or w == 1) 263 add = (u == 1) 264 if b == 0: 265 size = 4 266 else: 267 size = 1 268 if add: 269 addStr = "true" 270 else: 271 addStr = "false" 272 if imm: 273 newDecode = "return new %s(machInst, RD, RN," + \ 274 "%s, machInst.immed11_0);" 275 className = loadImmClassName(post, add, writeback, 276 size, False, user) 277 newDecode = newDecode % (className, addStr) 278 else: 279 newDecode = "return new %s(machInst, RD, RN, %s," + \ 280 "machInst.shiftSize," + \ 281 "machInst.shift, RM);" 282 className = loadRegClassName(post, add, writeback, 283 size, False, user) 284 newDecode = newDecode % (className, addStr) 285 decode_block += ''' 286 case %#x: 287 {%s} 288 break; 289 ''' % (buildPUBWLCase(p,u,b,w,1), newDecode) |
323 decode_block += ''' 324 default: 325 return new Unknown(machInst); 326 break; 327 }''' 328}}; 329 330def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{ --- 58 unchanged lines hidden --- | 290 decode_block += ''' 291 default: 292 return new Unknown(machInst); 293 break; 294 }''' 295}}; 296 297def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{ --- 58 unchanged lines hidden --- |