1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Gabe Black
42
43def format AddrMode2(imm) {{
44 if eval(imm):
45 imm = True
46 else:
47 imm = False
48
49 def buildPUBWLCase(p, u, b, w, l):
50 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
51
52 header_output = decoder_output = exec_output = ""
53 decode_block = "switch(PUBWL) {\n"
54
55 # Loop over all the values of p, u, b, w and l and build instructions and
56 # a decode block for them.
57 for p in (0, 1):
58 for u in (0, 1):
59 for b in (0, 1):
60 for w in (0, 1):
61 post = (p == 0)
62 user = (p == 0 and w == 1)
63 writeback = (p == 0 or w == 1)
64 add = (u == 1)
65 if b == 0:
66 size = 4
67 else:
68 size = 1
69 if add:
70 addStr = "true"
71 else:
72 addStr = "false"
73 if imm:
74 newDecode = "return new %s(machInst, RD, RN," + \
75 "%s, machInst.immed11_0);"
76 loadClass = loadImmClassName(post, add, writeback,
77 size, False, user)
78 storeClass = storeImmClassName(post, add, writeback,
79 size, False, user)
80 loadDecode = newDecode % (loadClass, addStr)
81 storeDecode = newDecode % (storeClass, addStr)
82 else:
83 newDecode = "return new %s(machInst, RD, RN, %s," + \
84 "machInst.shiftSize," + \
85 "machInst.shift, RM);"
86 loadClass = loadRegClassName(post, add, writeback,
87 size, False, user)
88 storeClass = storeRegClassName(post, add, writeback,
89 size, False, user)
90 loadDecode = newDecode % (loadClass, addStr)
91 storeDecode = newDecode % (storeClass, addStr)
92 decode = '''
93 case %#x:
94 {%s}
95 break;
96 '''
97 decode_block += decode % \
98 (buildPUBWLCase(p,u,b,w,1), loadDecode)
99 decode_block += decode % \
100 (buildPUBWLCase(p,u,b,w,0), storeDecode)
101 decode_block += '''
102 default:
103 return new Unknown(machInst);
104 break;
105 }'''
106}};
107
108def format AddrMode3() {{
109 decode = '''
110 {
111 const uint32_t op1 = bits(machInst, 24, 20);
112 const uint32_t op2 = bits(machInst, 6, 5);
113 const uint32_t puiw = bits(machInst, 24, 21);
114 const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0;
115 switch (op2) {
116 case 0x1:
117 if (op1 & 0x1) {
118 %(ldrh)s
119 } else {
120 %(strh)s
121 }
122 case 0x2:
123 if (op1 & 0x1) {
124 %(ldrsb)s
125 } else if ((RT %% 2) == 0) {
126 %(ldrd)s
127 } else {
128 return new Unknown(machInst);
129 }
130 case 0x3:
131 if (op1 & 0x1) {
132 %(ldrsh)s
133 } else {
134 %(strd)s
135 }
136 default:
137 return new Unknown(machInst);
138 }
139 }
140 '''
141
142 def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False):
143 post = (p == 0)
144 user = (p == 0 and w == 1)
145 writeback = (p == 0 or w == 1)
146 add = (u == 1)
147 caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0)
148 decode = '''
149 case %#x:
150 return new '''% caseVal
151 if add:
152 addStr = "true"
153 else:
154 addStr = "false"
155 if d:
156 dests = "RT & ~1, RT | 1"
157 else:
158 dests = "RT"
159 if i:
160 if load:
161 if d:
162 className = loadDoubleImmClassName(post, add, writeback)
163 else:
164 className = loadImmClassName(post, add, writeback, \
165 size=size, sign=sign, \
166 user=user)
167 else:
168 if d:
169 className = storeDoubleImmClassName(post, add, writeback)
170 else:
171 className = storeImmClassName(post, add, writeback, \
172 size=size, sign=sign, \
173 user=user)
174 decode += ("%s(machInst, %s, RN, %s, imm);\n" % \
175 (className, dests, addStr))
176 else:
177 if load:
178 if d:
179 className = loadDoubleRegClassName(post, add, writeback)
180 else:
181 className = loadRegClassName(post, add, writeback, \
182 size=size, sign=sign, \
183 user=user)
184 else:
185 if d:
186 className = storeDoubleRegClassName(post, add, writeback)
187 else:
188 className = storeRegClassName(post, add, writeback, \
189 size=size, sign=sign, \
190 user=user)
191 decode += ("%s(machInst, %s, RN, %s, 0, LSL, RM);\n" % \
192 (className, dests, addStr))
193 return decode
194
195 def decodePuiw(load, d, size=4, sign=False):
196 global decodePuiwCase
197 decode = "switch (puiw) {\n"
198 for p in (0, 1):
199 for u in (0, 1):
200 for i in (0, 1):
201 for w in (0, 1):
202 decode += decodePuiwCase(load, d, p, u, i, w,
203 size, sign)
204 decode += '''
205 default:
206 return new Unknown(machInst);
207 }
208 '''
209 return decode
210
211 subs = {
212 "ldrh" : decodePuiw(True, False, size=2),
213 "strh" : decodePuiw(False, False, size=2),
214 "ldrsb" : decodePuiw(True, False, size=1, sign=True),
215 "ldrd" : decodePuiw(True, True),
216 "ldrsh" : decodePuiw(True, False, size=2, sign=True),
217 "strd" : decodePuiw(False, True)
218 }
219 decode_block = decode % subs
220}};
221
222def format ArmSyncMem() {{
223 decode_block = '''
224 {
225 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
226 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
227 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
228 switch (PUBWL) {
229 case 0x18:
230 return new %(strex)s(machInst, rt, rt2, rn, true, 0);
231 case 0x19:
232 return new %(ldrex)s(machInst, rt, rn, true, 0);
233 case 0x1a:
234 return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0);
235 case 0x1b:
236 return new %(ldrexd)s(machInst, rt, rt + 1, rn, true, 0);
237 case 0x1c:
238 return new %(strexb)s(machInst, rt, rt2, rn, true, 0);
239 case 0x1d:
240 return new %(ldrexb)s(machInst, rt, rn, true, 0);
241 case 0x1e:
242 return new %(strexh)s(machInst, rt, rt2, rn, true, 0);
243 case 0x1f:
244 return new %(ldrexh)s(machInst, rt, rn, true, 0);
245 default:
246 return new Unknown(machInst);
247 }
248 }
249 ''' % {
250 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
251 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
252 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2),
253 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False),
254 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4),
255 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1),
256 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2),
257 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False)
258 }
259}};
260
261def format Thumb32SrsRfe() {{
262 decode_block = '''
263 {
264 const bool wb = (bits(machInst, 21) == 1);
265 const bool add = (bits(machInst, 24, 23) == 0x3);
266 if (bits(machInst, 20) == 1) {
267 // post == add
268 const IntRegIndex rn =
269 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
270 if (!add && !wb) {
271 return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb);
272 } else if (add && !wb) {
273 return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb);
274 } else if (!add && wb) {
275 return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb);
276 } else {
277 return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb);
278 }
279 } else {
280 const uint32_t mode = bits(machInst, 4, 0);
281 // We check at decode stage if the mode exists even
282 // if the checking is re-done by Srs::execute.
283 // This is done because we will otherwise panic if
284 // trying to read the banked stack pointer of an
285 // unrecognized mode.
286 if (unknownMode32((OperatingMode)mode))
287 return new Unknown(machInst);
288 if (!add && !wb) {
289 return new %(srs)s(machInst, mode,
290 SrsOp::DecrementBefore, wb);
291 } else if (add && !wb) {
292 return new %(srs_u)s(machInst, mode,
293 SrsOp::IncrementAfter, wb);
294 } else if (!add && wb) {
295 return new %(srs_w)s(machInst, mode,
296 SrsOp::DecrementBefore, wb);
297 } else {
298 return new %(srs_uw)s(machInst, mode,
299 SrsOp::IncrementAfter, wb);
300 }
301 }
302 }
303 ''' % {
304 "rfe" : "RFE_" + loadImmClassName(False, False, False, 8),
305 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
306 "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8),
307 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
308 "srs" : "SRS_" + storeImmClassName(False, False, False, 8),
309 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
310 "srs_w" : "SRS_" + storeImmClassName(False, False, True, 8),
311 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8)
312 }
313}};
314
315def format Thumb32LdrStrDExTbh() {{
316 decode_block = '''
317 {
318 const uint32_t op1 = bits(machInst, 24, 23);
319 const uint32_t op2 = bits(machInst, 21, 20);
320 const uint32_t op3 = bits(machInst, 7, 4);
321 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
322 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
323 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
324 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
325 const uint32_t imm8 = bits(machInst, 7, 0);
326 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
327 if (op1 == 0) {
328 const uint32_t imm = bits(machInst, 7, 0) << 2;
329 if (op2 == 0) {
330 return new %(strex)s(machInst, rt2, rt, rn, true, imm);
331 } else {
332 return new %(ldrex)s(machInst, rt, rn, true, imm);
333 }
334 } else {
335 if (op2 == 0) {
336 switch (op3) {
337 case 0x4:
338 return new %(strexb)s(machInst, rd, rt, rn, true, 0);
339 case 0x5:
340 return new %(strexh)s(machInst, rd, rt, rn, true, 0);
341 case 0x7:
342 return new %(strexd)s(machInst, rd, rt,
343 rt2, rn, true, 0);
344 default:
345 return new Unknown(machInst);
346 }
347 } else {
348 switch (op3) {
349 case 0x0:
350 return new Tbb(machInst, rn, rd);
351 case 0x1:
352 return new Tbh(machInst, rn, rd);
353 case 0x4:
354 return new %(ldrexb)s(machInst, rt, rn, true, 0);
355 case 0x5:
356 return new %(ldrexh)s(machInst, rt, rn, true, 0);
357 case 0x7:
358 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0);
359 default:
360 return new Unknown(machInst);
361 }
362 }
363 }
364 } else {
365 const uint32_t puw = (bits(machInst, 24, 23) << 1) |
366 bits(machInst, 21);
367 const uint32_t dimm = imm8 << 2;
368 if (bits(op2, 0) == 0) {
369 switch (puw) {
370 case 0x1:
371 return new %(strd_w)s(machInst, rt, rt2, rn, false, dimm);
372 case 0x3:
373 return new %(strd_uw)s(machInst, rt, rt2, rn, true, dimm);
374 case 0x4:
375 return new %(strd_p)s(machInst, rt, rt2, rn, false, dimm);
376 case 0x5:
377 return new %(strd_pw)s(machInst, rt, rt2, rn, false, dimm);
378 case 0x6:
379 return new %(strd_pu)s(machInst, rt, rt2, rn, true, dimm);
380 case 0x7:
381 return new %(strd_puw)s(machInst, rt, rt2, rn, true, dimm);
382 default:
383 return new Unknown(machInst);
384 }
385 } else {
386 switch (puw) {
387 case 0x1:
388 return new %(ldrd_w)s(machInst, rt, rt2, rn, false, dimm);
389 case 0x3:
390 return new %(ldrd_uw)s(machInst, rt, rt2, rn, true, dimm);
391 case 0x4:
392 return new %(ldrd_p)s(machInst, rt, rt2, rn, false, dimm);
393 case 0x5:
394 return new %(ldrd_pw)s(machInst, rt, rt2, rn, false, dimm);
395 case 0x6:
396 return new %(ldrd_pu)s(machInst, rt, rt2, rn, true, dimm);
397 case 0x7:
398 return new %(ldrd_puw)s(machInst, rt, rt2, rn, true, dimm);
399 default:
400 return new Unknown(machInst);
401 }
402 }
403 }
404 }
405 ''' % {
406 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
407 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
408 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2),
409 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False),
410 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4),
411 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1),
412 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2),
413 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False),
414 "ldrd_w" : loadDoubleImmClassName(True, False, True),
415 "ldrd_uw" : loadDoubleImmClassName(True, True, True),
416 "ldrd_p" : loadDoubleImmClassName(False, False, False),
417 "ldrd_pw" : loadDoubleImmClassName(False, False, True),
418 "ldrd_pu" : loadDoubleImmClassName(False, True, False),
419 "ldrd_puw" : loadDoubleImmClassName(False, True, True),
420 "strd_w" : storeDoubleImmClassName(True, False, True),
421 "strd_uw" : storeDoubleImmClassName(True, True, True),
422 "strd_p" : storeDoubleImmClassName(False, False, False),
423 "strd_pw" : storeDoubleImmClassName(False, False, True),
424 "strd_pu" : storeDoubleImmClassName(False, True, False),
425 "strd_puw" : storeDoubleImmClassName(False, True, True)
426 }
427}};
428
429def format Thumb32LoadWord() {{
430 decode = '''
431 {
432 uint32_t op1 = bits(machInst, 24, 23);
433 if (bits(op1, 1) == 0) {
434 uint32_t op2 = bits(machInst, 11, 6);
435 if (HTRN == 0xF) {
436 if (UP) {
437 return new %(literal_u)s(machInst, RT, INTREG_PC,
438 true, IMMED_11_0);
439 } else {
440 return new %(literal)s(machInst, RT, INTREG_PC,
441 false, IMMED_11_0);
442 }
443 } else if (op1 == 0x1) {
444 return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0);
445 } else if (op2 == 0) {
446 return new %(register)s(machInst, RT, RN, UP,
447 bits(machInst, 5, 4), LSL, RM);
448 } else if ((op2 & 0x3c) == 0x38) {
449 return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0);
450 } else if ((op2 & 0x3c) == 0x30 || //P
451 (op2 & 0x24) == 0x24) { //W
452 uint32_t puw = bits(machInst, 10, 8);
453 uint32_t imm = IMMED_7_0;
454 switch (puw) {
455 case 0:
456 case 2:
457 // If we're here, either P or W must have been set.
458 panic("Neither P or W set, but that "
459 "shouldn't be possible.\\n");
460 case 1:
461 return new %(imm_w)s(machInst, RT, RN, false, imm);
462 case 3:
463 return new %(imm_uw)s(machInst, RT, RN, true, imm);
464 case 4:
465 return new %(imm_p)s(machInst, RT, RN, false, imm);
466 case 5:
467 return new %(imm_pw)s(machInst, RT, RN, false, imm);
468 case 6:
469 return new %(imm_pu)s(machInst, RT, RN, true, imm);
470 case 7:
471 return new %(imm_puw)s(machInst, RT, RN, true, imm);
472 }
473 }
474 return new Unknown(machInst);
475 } else {
476 return new Unknown(machInst);
477 }
478 }
479 '''
480 classNames = {
481 "literal_u" : loadImmClassName(False, True, False),
482 "literal" : loadImmClassName(False, False, False),
483 "register" : loadRegClassName(False, True, False),
484 "ldrt" : loadImmClassName(False, True, False, user=True),
485 "imm_w" : loadImmClassName(True, False, True),
486 "imm_uw" : loadImmClassName(True, True, True),
487 "imm_p" : loadImmClassName(False, False, False),
488 "imm_pw" : loadImmClassName(False, False, True),
489 "imm_pu" : loadImmClassName(False, True, False),
490 "imm_puw" : loadImmClassName(False, True, True)
491 }
492 decode_block = decode % classNames
493}};
494
495def format Thumb32StoreSingle() {{
496 def buildPuwDecode(size):
497 puwDecode = '''
498 {
499 uint32_t puw = bits(machInst, 10, 8);
500 uint32_t imm = IMMED_7_0;
501 switch (puw) {
502 case 0:
503 case 2:
504 // If we're here, either P or W must have been set.
505 panic("Neither P or W set, but that "
506 "shouldn't be possible.\\n");
507 case 1:
508 return new %(imm_w)s(machInst, RT, RN, false, imm);
509 case 3:
510 return new %(imm_uw)s(machInst, RT, RN, true, imm);
511 case 4:
512 return new %(imm_p)s(machInst, RT, RN, false, imm);
513 case 5:
514 return new %(imm_pw)s(machInst, RT, RN, false, imm);
515 case 6:
516 return new %(imm_pu)s(machInst, RT, RN, true, imm);
517 case 7:
518 return new %(imm_puw)s(machInst, RT, RN, true, imm);
519 default:
520 M5_UNREACHABLE;
521 }
522 }
523 '''
524 return puwDecode % {
525 "imm_w" : storeImmClassName(True, False, True, size=size),
526 "imm_uw" : storeImmClassName(True, True, True, size=size),
527 "imm_p" : storeImmClassName(False, False, False, size=size),
528 "imm_pw" : storeImmClassName(False, False, True, size=size),
529 "imm_pu" : storeImmClassName(False, True, False, size=size),
530 "imm_puw" : storeImmClassName(False, True, True, size=size)
531 }
532 decode = '''
533 {
534 uint32_t op1 = bits(machInst, 23, 21);
535 uint32_t op2 = bits(machInst, 11, 6);
536 bool op2Puw = ((op2 & 0x24) == 0x24 ||
537 (op2 & 0x3c) == 0x30);
538 if (RN == 0xf) {
539 return new Unknown(machInst);
540 }
541 if (op1 == 4) {
542 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0);
543 } else if (op1 == 0 && op2Puw) {
544 %(strb_puw)s;
545 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) {
546 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0);
547 } else if (op1 == 0 && op2 == 0) {
548 return new %(strb_reg)s(machInst, RT, RN, true,
549 bits(machInst, 5, 4), LSL, RM);
550 } else if (op1 == 5) {
551 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0);
552 } else if (op1 == 1 && op2Puw) {
553 %(strh_puw)s;
554 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) {
555 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0);
556 } else if (op1 == 1 && op2 == 0) {
557 return new %(strh_reg)s(machInst, RT, RN, true,
558 bits(machInst, 5, 4), LSL, RM);
559 } else if (op1 == 6) {
560 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0);
561 } else if (op1 == 2 && op2Puw) {
562 %(str_puw)s;
563 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) {
564 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0);
565 } else if (op1 == 2 && op2 == 0) {
566 return new %(str_reg)s(machInst, RT, RN, true,
567 bits(machInst, 5, 4), LSL, RM);
568 } else {
569 return new Unknown(machInst);
570 }
571 }
572 '''
573 classNames = {
574 "strb_imm" : storeImmClassName(False, True, False, size=1),
575 "strb_puw" : buildPuwDecode(1),
576 "strbt" : storeImmClassName(False, True, False, user=True, size=1),
577 "strb_reg" : storeRegClassName(False, True, False, size=1),
578 "strh_imm" : storeImmClassName(False, True, False, size=2),
579 "strh_puw" : buildPuwDecode(2),
580 "strht" : storeImmClassName(False, True, False, user=True, size=2),
581 "strh_reg" : storeRegClassName(False, True, False, size=2),
582 "str_imm" : storeImmClassName(False, True, False),
583 "str_puw" : buildPuwDecode(4),
584 "strt" : storeImmClassName(False, True, False, user=True),
585 "str_reg" : storeRegClassName(False, True, False)
586 }
587 decode_block = decode % classNames
588}};
589
590def format LoadByteMemoryHints() {{
591 decode = '''
592 {
593 const uint32_t op1 = bits(machInst, 24, 23);
594 const uint32_t op2 = bits(machInst, 11, 6);
595 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
596 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
597 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
598 const uint32_t imm12 = bits(machInst, 11, 0);
599 const uint32_t imm8 = bits(machInst, 7, 0);
600 bool pldw = bits(machInst, 21);
601 const uint32_t imm2 = bits(machInst, 5, 4);
602 if (rn == 0xf) {
603 if (rt == 0xf) {
604 const bool add = bits(machInst, 23);
605 if (bits(op1, 1) == 1) {
606 if (add) {
607 return new %(pli_iulit)s(machInst, INTREG_ZERO,
608 INTREG_PC, true, imm12);
609 } else {
610 return new %(pli_ilit)s(machInst, INTREG_ZERO,
611 INTREG_PC, false, imm12);
612 }
613 } else {
614 if (add) {
615 return new %(pld_iulit)s(machInst, INTREG_ZERO,
616 INTREG_PC, true, imm12);
617 } else {
618 return new %(pld_ilit)s(machInst, INTREG_ZERO,
619 INTREG_PC, false, imm12);
620 }
621 }
622 } else {
623 if (bits(op1, 1) == 1) {
624 if (bits(machInst, 23)) {
625 return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC,
626 true, imm12);
627 } else {
628 return new %(ldrsb_lit)s(machInst, rt, INTREG_PC,
629 false, imm12);
630 }
631 } else {
632 if (bits(machInst, 23)) {
633 return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC,
634 true, imm12);
635 } else {
636 return new %(ldrb_lit)s(machInst, rt, INTREG_PC,
637 false, imm12);
638 }
639 }
640 }
641 } else if (rt == 0xf) {
642 switch (op1) {
643 case 0x0:
644 if (op2 == 0x0) {
645 if (pldw) {
646 return new %(pldw_radd)s(machInst, INTREG_ZERO,
647 rn, true, imm2, LSL, rm);
648 } else {
649 return new %(pld_radd)s(machInst, INTREG_ZERO,
650 rn, true, imm2, LSL, rm);
651 }
652 } else if (bits(op2, 5, 2) == 0xc) {
653 if (pldw) {
654 return new %(pldw_isub)s(machInst, INTREG_ZERO,
655 rn, false, imm8);
656 } else {
657 return new %(pld_isub)s(machInst, INTREG_ZERO,
658 rn, false, imm8);
659 }
660 }
661 break;
662 case 0x1:
663 if (pldw) {
664 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
665 rn, true, imm12);
666 } else {
667 return new %(pld_iadd)s(machInst, INTREG_ZERO,
668 rn, true, imm12);
669 }
670 case 0x2:
671 if (op2 == 0x0) {
672 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
673 true, imm2, LSL, rm);
674 } else if (bits(op2, 5, 2) == 0xc) {
675 return new %(pli_ilit)s(machInst, INTREG_ZERO,
676 INTREG_PC, false, imm8);
677 }
678 break;
679 case 0x3:
680 return new %(pli_iulit)s(machInst, INTREG_ZERO,
681 INTREG_PC, true, imm12);
682 }
683 return new Unknown(machInst);
684 } else {
685 switch (op1) {
686 case 0x0:
687 if (op2 == 0) {
688 return new %(ldrb_radd)s(machInst, rt, rn, true,
689 imm2, LSL, rm);
690 } else if (bits(op2, 5, 2) == 0xe) {
691 return new %(ldrbt)s(machInst, rt, rn, true, imm8);
692 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
693 const uint32_t puw = bits(machInst, 10, 8);
694 switch (puw) {
695 case 0x1:
696 return new %(ldrb_iw)s(machInst, rt,
697 rn, false, imm8);
698 case 0x3:
699 return new %(ldrb_iuw)s(machInst, rt,
700 rn, true, imm8);
701 case 0x4:
702 return new %(ldrb_ip)s(machInst, rt,
703 rn, false, imm8);
704 case 0x5:
705 return new %(ldrb_ipw)s(machInst, rt,
706 rn, false, imm8);
707 case 0x7:
708 return new %(ldrb_ipuw)s(machInst, rt,
709 rn, true, imm8);
710 }
711 }
712 break;
713 case 0x1:
714 return new %(ldrb_iadd)s(machInst, rt, rn, true, imm12);
715 case 0x2:
716 if (op2 == 0) {
717 return new %(ldrsb_radd)s(machInst, rt, rn, true,
718 imm2, LSL, rm);
719 } else if (bits(op2, 5, 2) == 0xe) {
720 return new %(ldrsbt)s(machInst, rt, rn, true, imm8);
721 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
722 const uint32_t puw = bits(machInst, 10, 8);
723 switch (puw) {
724 case 0x1:
725 return new %(ldrsb_iw)s(machInst, rt,
726 rn, false, imm8);
727 case 0x3:
728 return new %(ldrsb_iuw)s(machInst, rt,
729 rn, true, imm8);
730 case 0x4:
731 return new %(ldrsb_ip)s(machInst, rt,
732 rn, false, imm8);
733 case 0x5:
734 return new %(ldrsb_ipw)s(machInst, rt,
735 rn, false, imm8);
736 case 0x7:
737 return new %(ldrsb_ipuw)s(machInst, rt,
738 rn, true, imm8);
739 }
740 }
741 break;
742 case 0x3:
743 return new %(ldrsb_iadd)s(machInst, rt, rn, true, imm12);
744 }
745 return new Unknown(machInst);
746 }
747 }
748 '''
749 substDict = {
750 "ldrsb_lit_u" : loadImmClassName(False, True, False, 1, True),
751 "ldrsb_lit" : loadImmClassName(False, False, False, 1, True),
752 "ldrb_lit_u" : loadImmClassName(False, True, False, 1),
753 "ldrb_lit" : loadImmClassName(False, False, False, 1),
754 "ldrsb_radd" : loadRegClassName(False, True, False, 1, True),
755 "ldrb_radd" : loadRegClassName(False, True, False, 1),
756 "ldrsb_iw" : loadImmClassName(True, False, True, 1, True),
757 "ldrsb_iuw" : loadImmClassName(True, True, True, 1, True),
758 "ldrsb_ip" : loadImmClassName(False, False, False, 1, True),
759 "ldrsb_ipw" : loadImmClassName(False, False, True, 1, True),
760 "ldrsb_ipuw" : loadImmClassName(False, True, True, 1, True),
761 "ldrsb_iadd" : loadImmClassName(False, True, False, 1, True),
762 "ldrb_iw" : loadImmClassName(True, False, True, 1),
763 "ldrb_iuw" : loadImmClassName(True, True, True, 1),
764 "ldrb_ip" : loadImmClassName(False, False, False, 1),
765 "ldrb_ipw" : loadImmClassName(False, False, True, 1),
766 "ldrb_ipuw" : loadImmClassName(False, True, True, 1),
767 "ldrb_iadd" : loadImmClassName(False, True, False, 1),
768 "ldrbt" : loadImmClassName(False, True, False, 1, user=True),
769 "ldrsbt" : loadImmClassName(False, True, False, 1, True, user=True),
770 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
771 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
772 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
773 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
774 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
775 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
776 "pld_iulit" : "PLD_" + loadImmClassName(False, True, False, 1),
777 "pld_ilit" : "PLD_" + loadImmClassName(False, False, False, 1),
778 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1),
779 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1),
780 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
781 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1),
782 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1)
783 }
784 decode_block = decode % substDict
785}};
786
787def format LoadHalfwordMemoryHints() {{
788 decode = '''
789 {
790 const uint32_t op1 = bits(machInst, 24, 23);
791 const uint32_t op2 = bits(machInst, 11, 6);
792 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
793 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
794 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
795 const uint32_t imm12 = bits(machInst, 11, 0);
796 const uint32_t imm8 = bits(machInst, 7, 0);
797 bool pldw = bits(machInst, 21);
798 const uint32_t imm2 = bits(machInst, 5, 4);
799 if (rn == 0xf) {
800 if (rt == 0xf) {
801 if (bits(op1, 1) == 1) {
802 // Unallocated memory hint
803 return new NopInst(machInst);
804 } else {
805 return new Unknown(machInst);
806 }
807 } else {
808 if (bits(op1, 1) == 1) {
809 if (bits(machInst, 23)) {
810 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC,
811 true, imm12);
812 } else {
813 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC,
814 false, imm12);
815 }
816 } else {
817 if (bits(machInst, 23)) {
818 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC,
819 true, imm12);
820 } else {
821 return new %(ldrh_lit)s(machInst, rt, INTREG_PC,
822 false, imm12);
823 }
824 }
825 }
826 } else if (rt == 0xf) {
827 switch (op1) {
828 case 0x0:
829 if (op2 == 0x0) {
830 if (pldw) {
831 return new %(pldw_radd)s(machInst, INTREG_ZERO,
832 rn, true, imm2, LSL, rm);
833 } else {
834 return new %(pld_radd)s(machInst, INTREG_ZERO,
835 rn, true, imm2, LSL, rm);
836 }
837 } else if (bits(op2, 5, 2) == 0xc) {
838 if (pldw) {
839 return new %(pldw_isub)s(machInst, INTREG_ZERO,
840 rn, false, imm8);
841 } else {
842 return new %(pld_isub)s(machInst, INTREG_ZERO,
843 rn, false, imm8);
844 }
845 }
846 break;
847 case 0x1:
848 if (pldw) {
849 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
850 rn, true, imm12);
851 } else {
852 return new %(pld_iadd)s(machInst, INTREG_ZERO,
853 rn, true, imm12);
854 }
855 case 0x2:
856 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) {
857 // Unallocated memory hint
858 return new NopInst(machInst);
859 }
860 break;
861 case 0x3:
862 return new NopInst(machInst);
863 }
864 return new Unknown(machInst);
865 } else {
866 switch (op1) {
867 case 0x0:
868 if (op2 == 0) {
869 return new %(ldrh_radd)s(machInst, rt, rn, true,
870 imm2, LSL, rm);
871 } else if (bits(op2, 5, 2) == 0xe) {
872 return new %(ldrht)s(machInst, rt, rn, true, imm8);
873 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
874 const uint32_t puw = bits(machInst, 10, 8);
875 switch (puw) {
876 case 0x1:
877 return new %(ldrh_iw)s(machInst, rt,
878 rn, false, imm8);
879 case 0x3:
880 return new %(ldrh_iuw)s(machInst, rt,
881 rn, true, imm8);
882 case 0x4:
883 return new %(ldrh_ip)s(machInst, rt,
884 rn, false, imm8);
885 case 0x5:
886 return new %(ldrh_ipw)s(machInst, rt,
887 rn, false, imm8);
888 case 0x7:
889 return new %(ldrh_ipuw)s(machInst, rt,
890 rn, true, imm8);
891 }
892 }
893 break;
894 case 0x1:
895 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12);
896 case 0x2:
897 if (op2 == 0) {
898 return new %(ldrsh_radd)s(machInst, rt, rn, true,
899 imm2, LSL, rm);
900 } else if (bits(op2, 5, 2) == 0xe) {
901 return new %(ldrsht)s(machInst, rt, rn, true, imm8);
902 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
903 const uint32_t puw = bits(machInst, 10, 8);
904 switch (puw) {
905 case 0x1:
906 return new %(ldrsh_iw)s(machInst, rt,
907 rn, false, imm8);
908 case 0x3:
909 return new %(ldrsh_iuw)s(machInst, rt,
910 rn, true, imm8);
911 case 0x4:
912 return new %(ldrsh_ip)s(machInst, rt,
913 rn, false, imm8);
914 case 0x5:
915 return new %(ldrsh_ipw)s(machInst, rt,
916 rn, false, imm8);
917 case 0x7:
918 return new %(ldrsh_ipuw)s(machInst, rt,
919 rn, true, imm8);
920 }
921 }
922 break;
923 case 0x3:
924 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12);
925 }
926 return new Unknown(machInst);
927 }
928 }
929 '''
930 substDict = {
931 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True),
932 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True),
933 "ldrh_lit_u" : loadImmClassName(False, True, False, 2),
934 "ldrh_lit" : loadImmClassName(False, False, False, 2),
935 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True),
936 "ldrh_radd" : loadRegClassName(False, True, False, 2),
937 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True),
938 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True),
939 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True),
940 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True),
941 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True),
942 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True),
943 "ldrh_iw" : loadImmClassName(True, False, True, 2),
944 "ldrh_iuw" : loadImmClassName(True, True, True, 2),
945 "ldrh_ip" : loadImmClassName(False, False, False, 2),
946 "ldrh_ipw" : loadImmClassName(False, False, True, 2),
947 "ldrh_ipuw" : loadImmClassName(False, True, True, 2),
948 "ldrh_iadd" : loadImmClassName(False, True, False, 2),
949 "ldrht" : loadImmClassName(False, True, False, 2, user=True),
950 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True),
951 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
952 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
953 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
954 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
955 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
956 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1)
957 }
958 decode_block = decode % substDict
959}};
960
961def format Thumb16MemReg() {{
962 decode = '''
963 {
964 const uint32_t opb = bits(machInst, 11, 9);
965 const uint32_t rt = bits(machInst, 2, 0);
966 const uint32_t rn = bits(machInst, 5, 3);
967 const uint32_t rm = bits(machInst, 8, 6);
968 switch (opb) {
969 case 0x0:
970 return new %(str)s(machInst, rt, rn, true, 0, LSL, rm);
971 case 0x1:
972 return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm);
973 case 0x2:
974 return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm);
975 case 0x3:
976 return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm);
977 case 0x4:
978 return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm);
979 case 0x5:
980 return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm);
981 case 0x6:
982 return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm);
983 case 0x7:
984 return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm);
985 default:
986 M5_UNREACHABLE;
987 }
988 }
989 '''
990 classNames = {
991 "str" : storeRegClassName(False, True, False),
992 "strh" : storeRegClassName(False, True, False, size=2),
993 "strb" : storeRegClassName(False, True, False, size=1),
994 "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1),
995 "ldr" : loadRegClassName(False, True, False),
996 "ldrh" : loadRegClassName(False, True, False, size=2),
997 "ldrb" : loadRegClassName(False, True, False, size=1),
998 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2),
999 }
1000 decode_block = decode % classNames
1001}};
1002
1003def format Thumb16MemImm() {{
1004 decode = '''
1005 {
1006 const uint32_t opa = bits(machInst, 15, 12);
1007 const uint32_t opb = bits(machInst, 11, 9);
1008 const uint32_t lrt = bits(machInst, 2, 0);
1009 const uint32_t lrn = bits(machInst, 5, 3);
1010 const uint32_t hrt = bits(machInst, 10, 8);
1011 const uint32_t imm5 = bits(machInst, 10, 6);
1012 const uint32_t imm8 = bits(machInst, 7, 0);
1013 const bool load = bits(opb, 2);
1014 switch (opa) {
1015 case 0x6:
1016 if (load) {
1017 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2);
1018 } else {
1019 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2);
1020 }
1021 case 0x7:
1022 if (load) {
1023 return new %(ldrb)s(machInst, lrt, lrn, true, imm5);
1024 } else {
1025 return new %(strb)s(machInst, lrt, lrn, true, imm5);
1026 }
1027 case 0x8:
1028 if (load) {
1029 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1);
1030 } else {
1031 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1);
1032 }
1033 case 0x9:
1034 if (load) {
1035 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
1036 } else {
1037 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
1038 }
1039 default:
1040 return new Unknown(machInst);
1041 }
1042 }
1043 '''
1044 classNames = {
1045 "ldr" : loadImmClassName(False, True, False),
1046 "str" : storeImmClassName(False, True, False),
1047 "ldrh" : loadImmClassName(False, True, False, size=2),
1048 "strh" : storeImmClassName(False, True, False, size=2),
1049 "ldrb" : loadImmClassName(False, True, False, size=1),
1050 "strb" : storeImmClassName(False, True, False, size=1),
1051 }
1052 decode_block = decode % classNames
1053}};
1054
1055def format Thumb16MemLit() {{
1056 decode_block = '''
1057 {
1058 const uint32_t rt = bits(machInst, 10, 8);
1059 const uint32_t imm8 = bits(machInst, 7, 0);
1060 return new %s(machInst, rt, INTREG_PC, true, imm8 << 2);
1061 }
1062 ''' % loadImmClassName(False, True, False)
1063}};
1064