macromem.isa (6725:c469a9365a4a) macromem.isa (6726:a5322e816a2a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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175
176def template MacroStoreConstructor {{
177inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
178 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
179{
180 %(constructor)s;
181 uint32_t regs = reglist;
182 uint32_t addr = 0;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 166 unchanged lines hidden (view full) ---

175
176def template MacroStoreConstructor {{
177inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
178 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
179{
180 %(constructor)s;
181 uint32_t regs = reglist;
182 uint32_t addr = 0;
183 bool up = machInst.puswl.up;
183
184 if (!up)
185 addr = (ones << 2) - 4;
186
184
185 if (!up)
186 addr = (ones << 2) - 4;
187
187 if (prepost)
188 if (machInst.puswl.prepost)
188 addr += 4;
189
190 // Add 0 to Rn and stick it in ureg0.
191 // This is equivalent to a move.
192 microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
193
194 unsigned reg = 0;
195 for (int i = 1; i < ones + 1; i++) {
196 // Find the next register.
197 while (!bits(regs, reg))
198 reg++;
199 replaceBits(regs, reg, 0);
200
189 addr += 4;
190
191 // Add 0 to Rn and stick it in ureg0.
192 // This is equivalent to a move.
193 microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
194
195 unsigned reg = 0;
196 for (int i = 1; i < ones + 1; i++) {
197 // Find the next register.
198 while (!bits(regs, reg))
199 reg++;
200 replaceBits(regs, reg, 0);
201
201 if (loadop)
202 microOps[i] = new MicroLdrUop(machInst, reg, INTREG_UREG0, addr);
203 else
204 microOps[i] = new MicroStrUop(machInst, reg, INTREG_UREG0, addr);
202 unsigned regIdx = reg;
203 if (machInst.puswl.psruser) {
204 regIdx = intRegForceUser(regIdx);
205 }
205
206
207 if (machInst.puswl.loadOp) {
208 microOps[i] =
209 new MicroLdrUop(machInst, regIdx, INTREG_UREG0, addr);
210 } else {
211 microOps[i] =
212 new MicroStrUop(machInst, regIdx, INTREG_UREG0, addr);
213 }
214
206 if (up)
207 addr += 4;
208 else
209 addr -= 4;
210 }
211
212 StaticInstPtr &lastUop = microOps[numMicroops - 1];
215 if (up)
216 addr += 4;
217 else
218 addr -= 4;
219 }
220
221 StaticInstPtr &lastUop = microOps[numMicroops - 1];
213 if (writeback) {
222 if (machInst.puswl.writeback) {
214 if (up) {
215 lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
216 } else {
217 lastUop = new MicroSubiUop(machInst, RN, RN, ones * 4);
218 }
219 }
220 lastUop->setLastMicroop();
221}

--- 111 unchanged lines hidden --- 		223 if (up) {
224 lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
225 } else {
226 lastUop = new MicroSubiUop(machInst, RN, RN, ones * 4);
227 }
228 }
229 lastUop->setLastMicroop();
230}

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