macromem.isa (6717:07546255fb03) macromem.isa (6725:c469a9365a4a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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173};
174}};
175
176def template MacroStoreConstructor {{
177inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
178 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
179{
180 %(constructor)s;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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173};
174}};
175
176def template MacroStoreConstructor {{
177inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
178 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
179{
180 %(constructor)s;
181 uint32_t regs_to_handle = reglist;
182 uint32_t start_addr = 0;
181 uint32_t regs = reglist;
182 uint32_t addr = 0;
183
183
184 switch (puswl)
185 {
186 case 0x00: // stmda
187 case 0x01: // L ldmda_l
188 case 0x02: // W stmda_w
189 case 0x03: // WL ldmda_wl
190 start_addr = (ones << 2) - 4;
191 break;
192 case 0x08: // U stmia_u
193 case 0x09: // U L ldmia_ul
194 case 0x0a: // U W stmia
195 case 0x0b: // U WL ldmia
196 start_addr = 0;
197 break;
198 case 0x10: // P stmdb
199 case 0x11: // P L ldmdb
200 case 0x12: // P W stmdb
201 case 0x13: // P WL ldmdb
202 start_addr = (ones << 2); // U-bit is already 0 for subtract
203 break;
204 case 0x18: // PU stmib
205 case 0x19: // PU L ldmib
206 case 0x1a: // PU W stmib
207 case 0x1b: // PU WL ldmib
208 start_addr = 4;
209 break;
210 default:
211 panic("Unhandled Load/Store Multiple Instruction, "
212 "puswl = 0x%x", (unsigned) puswl);
213 break;
214 }
184 if (!up)
185 addr = (ones << 2) - 4;
215
186
187 if (prepost)
188 addr += 4;
189
216 // Add 0 to Rn and stick it in ureg0.
217 // This is equivalent to a move.
218 microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
219
190 // Add 0 to Rn and stick it in ureg0.
191 // This is equivalent to a move.
192 microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
193
220 unsigned j = 0;
221 for (int i = 1; i < ones+1; i++) {
222 // Get next available bit for transfer
223 while (! ( regs_to_handle & (1<<j)))
224 j++;
225 regs_to_handle &= ~(1<<j);
194 unsigned reg = 0;
195 for (int i = 1; i < ones + 1; i++) {
196 // Find the next register.
197 while (!bits(regs, reg))
198 reg++;
199 replaceBits(regs, reg, 0);
226
227 if (loadop)
200
201 if (loadop)
228 microOps[i] = new MicroLdrUop(machInst, j,
229 INTREG_UREG0, start_addr);
202 microOps[i] = new MicroLdrUop(machInst, reg, INTREG_UREG0, addr);
230 else
203 else
231 microOps[i] = new MicroStrUop(machInst, j,
232 INTREG_UREG0, start_addr);
204 microOps[i] = new MicroStrUop(machInst, reg, INTREG_UREG0, addr);
233
234 if (up)
205
206 if (up)
235 start_addr += 4;
207 addr += 4;
236 else
208 else
237 start_addr -= 4;
209 addr -= 4;
238 }
239
210 }
211
212 StaticInstPtr &lastUop = microOps[numMicroops - 1];
240 if (writeback) {
241 if (up) {
213 if (writeback) {
214 if (up) {
242 microOps[numMicroops-1] =
243 new MicroAddiUop(machInst, RN, RN, ones * 4);
215 lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
244 } else {
216 } else {
245 microOps[numMicroops-1] =
246 new MicroSubiUop(machInst, RN, RN, ones * 4);
217 lastUop = new MicroSubiUop(machInst, RN, RN, ones * 4);
247 }
248 }
218 }
219 }
249 microOps[numMicroops-1]->setLastMicroop();
220 lastUop->setLastMicroop();
250}
251
252}};
253
254def template MacroStoreExecute {{
255Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
256{
257 Fault fault = NoFault;

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282 else
283 start_addr = 0;
284
285 emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr);
286
287 if (writeback)
288 {
289 if (up) {
221}
222
223}};
224
225def template MacroStoreExecute {{
226Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
227{
228 Fault fault = NoFault;

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253 else
254 start_addr = 0;
255
256 emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr);
257
258 if (writeback)
259 {
260 if (up) {
290 microOps[numMicroops-1] =
261 microOps[numMicroops - 1] =
291 new MicroAddiUop(machInst, RN, RN, disp8);
292 } else {
262 new MicroAddiUop(machInst, RN, RN, disp8);
263 } else {
293 microOps[numMicroops-1] =
264 microOps[numMicroops - 1] =
294 new MicroSubiUop(machInst, RN, RN, disp8);
295 }
296 }
265 new MicroSubiUop(machInst, RN, RN, disp8);
266 }
267 }
297 microOps[numMicroops-1]->setLastMicroop();
268 microOps[numMicroops - 1]->setLastMicroop();
298}
299
300}};
301
302
303def template MacroFMConstructor {{
304inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
305 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

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313 else
314 start_addr = 0;
315
316 for (int i = 0; i < count; i++)
317 emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr);
318
319 if (writeback) {
320 if (up) {
269}
270
271}};
272
273
274def template MacroFMConstructor {{
275inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
276 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

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284 else
285 start_addr = 0;
286
287 for (int i = 0; i < count; i++)
288 emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr);
289
290 if (writeback) {
291 if (up) {
321 microOps[numMicroops-1] =
292 microOps[numMicroops - 1] =
322 new MicroAddiUop(machInst, RN, RN, disp8);
323 } else {
293 new MicroAddiUop(machInst, RN, RN, disp8);
294 } else {
324 microOps[numMicroops-1] =
295 microOps[numMicroops - 1] =
325 new MicroSubiUop(machInst, RN, RN, disp8);
326 }
327 }
296 new MicroSubiUop(machInst, RN, RN, disp8);
297 }
298 }
328 microOps[numMicroops-1]->setLastMicroop();
299 microOps[numMicroops - 1]->setLastMicroop();
329}
330}};
331
332
333def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
334 iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)
335 header_output = MacroStoreDeclare.subst(iop)
336 decoder_output = MacroStoreConstructor.subst(iop)

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301}};
302
303
304def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
305 iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)
306 header_output = MacroStoreDeclare.subst(iop)
307 decoder_output = MacroStoreConstructor.subst(iop)

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