macromem.isa (6308:46fcf4dc4c30) macromem.isa (6309:7f10d636910b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
30// Gabe Black
31
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
30// Gabe Black
31
32////////////////////////////////////////////////////////////////////
33//
34// Common microop templates
35//
32
36
37def template MicroConstructor {{
38 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
39 RegIndex _ura,
40 RegIndex _urb,
41 uint8_t _imm)
42 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
43 _ura, _urb, _imm)
44 {
45 %(constructor)s;
46 }
47}};
48
33////////////////////////////////////////////////////////////////////
34//
49////////////////////////////////////////////////////////////////////
50//
35// Integer = Integer op Immediate microops
51// Load/store microops
36//
37
52//
53
38def template MicroIntDeclare {{
54def template MicroMemDeclare {{
39 class %(class_name)s : public %(base_class)s
40 {
41 public:
42 %(class_name)s(ExtMachInst machInst,
43 RegIndex _ura, RegIndex _urb,
44 uint8_t _imm);
45 %(BasicExecDeclare)s
55 class %(class_name)s : public %(base_class)s
56 {
57 public:
58 %(class_name)s(ExtMachInst machInst,
59 RegIndex _ura, RegIndex _urb,
60 uint8_t _imm);
61 %(BasicExecDeclare)s
62 %(InitiateAccDeclare)s
63 %(CompleteAccDeclare)s
46 };
47}};
48
64 };
65}};
66
49def template MicroIntConstructor {{
50 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
51 RegIndex _ura,
52 RegIndex _urb,
53 uint8_t _imm)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
55 _ura, _urb, _imm)
67let {{
68 microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
69 'MicroMemOp',
70 {'memacc_code': 'Ra = Mem;',
71 'ea_code': 'EA = Rb + (UP ? imm : -imm);',
72 'predicate_test': predicateTest},
73 ['IsMicroop'])
74
75 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
76 'MicroMemOp',
77 {'memacc_code': 'Mem = Ra;',
78 'ea_code': 'EA = Rb + (UP ? imm : -imm);',
79 'predicate_test': predicateTest},
80 ['IsMicroop'])
81
82 header_output = MicroMemDeclare.subst(microLdrUopIop) + \
83 MicroMemDeclare.subst(microStrUopIop)
84 decoder_output = MicroConstructor.subst(microLdrUopIop) + \
85 MicroConstructor.subst(microStrUopIop)
86 exec_output = LoadExecute.subst(microLdrUopIop) + \
87 StoreExecute.subst(microStrUopIop) + \
88 LoadInitiateAcc.subst(microLdrUopIop) + \
89 StoreInitiateAcc.subst(microStrUopIop) + \
90 LoadCompleteAcc.subst(microLdrUopIop) + \
91 StoreCompleteAcc.subst(microStrUopIop)
92}};
93
94////////////////////////////////////////////////////////////////////
95//
96// Integer = Integer op Immediate microops
97//
98
99def template MicroIntDeclare {{
100 class %(class_name)s : public %(base_class)s
56 {
101 {
57 %(constructor)s;
58 }
102 public:
103 %(class_name)s(ExtMachInst machInst,
104 RegIndex _ura, RegIndex _urb,
105 uint8_t _imm);
106 %(BasicExecDeclare)s
107 };
59}};
60
61let {{
62 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
63 'MicroIntOp',
64 {'code': 'Ra = Rb + imm;',
65 'predicate_test': predicateTest},
66 ['IsMicroop'])
67
68 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
69 'MicroIntOp',
70 {'code': 'Ra = Rb - imm;',
71 'predicate_test': predicateTest},
72 ['IsMicroop'])
73
74 header_output = MicroIntDeclare.subst(microAddiUopIop) + \
75 MicroIntDeclare.subst(microSubiUopIop)
108}};
109
110let {{
111 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
112 'MicroIntOp',
113 {'code': 'Ra = Rb + imm;',
114 'predicate_test': predicateTest},
115 ['IsMicroop'])
116
117 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
118 'MicroIntOp',
119 {'code': 'Ra = Rb - imm;',
120 'predicate_test': predicateTest},
121 ['IsMicroop'])
122
123 header_output = MicroIntDeclare.subst(microAddiUopIop) + \
124 MicroIntDeclare.subst(microSubiUopIop)
76 decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
77 MicroIntConstructor.subst(microSubiUopIop)
125 decoder_output = MicroConstructor.subst(microAddiUopIop) + \
126 MicroConstructor.subst(microSubiUopIop)
78 exec_output = PredOpExecute.subst(microAddiUopIop) + \
79 PredOpExecute.subst(microSubiUopIop)
80}};
81
82////////////////////////////////////////////////////////////////////
83//
84// Macro Memory-format instructions
85//

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143
144 unsigned j = 0;
145 for (int i = 1; i < ones+1; i++) {
146 // Get next available bit for transfer
147 while (! ( regs_to_handle & (1<<j)))
148 j++;
149 regs_to_handle &= ~(1<<j);
150
127 exec_output = PredOpExecute.subst(microAddiUopIop) + \
128 PredOpExecute.subst(microSubiUopIop)
129}};
130
131////////////////////////////////////////////////////////////////////
132//
133// Macro Memory-format instructions
134//

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192
193 unsigned j = 0;
194 for (int i = 1; i < ones+1; i++) {
195 // Get next available bit for transfer
196 while (! ( regs_to_handle & (1<<j)))
197 j++;
198 regs_to_handle &= ~(1<<j);
199
151 microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr);
200 if (loadop)
201 microOps[i] = new MicroLdrUop(machInst, j, 17, start_addr);
202 else
203 microOps[i] = new MicroStrUop(machInst, j, 17, start_addr);
152
153 if (up)
154 start_addr += 4;
155 else
156 start_addr -= 4;
157 }
158
159 if (writeback) {

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205 if (up)
206 start_addr += 4;
207 else
208 start_addr -= 4;
209 }
210
211 if (writeback) {

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