macromem.isa (6304:a2af27fbc06c) macromem.isa (6308:46fcf4dc4c30)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
30// Gabe Black
30
31
32
31////////////////////////////////////////////////////////////////////
32//
33////////////////////////////////////////////////////////////////////
34//
35// Integer = Integer op Immediate microops
36//
37
38def template MicroIntDeclare {{
39 class %(class_name)s : public %(base_class)s
40 {
41 public:
42 %(class_name)s(ExtMachInst machInst,
43 RegIndex _ura, RegIndex _urb,
44 uint8_t _imm);
45 %(BasicExecDeclare)s
46 };
47}};
48
49def template MicroIntConstructor {{
50 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
51 RegIndex _ura,
52 RegIndex _urb,
53 uint8_t _imm)
54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
55 _ura, _urb, _imm)
56 {
57 %(constructor)s;
58 }
59}};
60
61let {{
62 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
63 'MicroIntOp',
64 {'code': 'Ra = Rb + imm;',
65 'predicate_test': predicateTest},
66 ['IsMicroop'])
67
68 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
69 'MicroIntOp',
70 {'code': 'Ra = Rb - imm;',
71 'predicate_test': predicateTest},
72 ['IsMicroop'])
73
74 header_output = MicroIntDeclare.subst(microAddiUopIop) + \
75 MicroIntDeclare.subst(microSubiUopIop)
76 decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
77 MicroIntConstructor.subst(microSubiUopIop)
78 exec_output = PredOpExecute.subst(microAddiUopIop) + \
79 PredOpExecute.subst(microSubiUopIop)
80}};
81
82////////////////////////////////////////////////////////////////////
83//
33// Macro Memory-format instructions
34//
35
36def template MacroStoreDeclare {{
37/**
38 * Static instructions class for a store multiple instruction
39 */
40class %(class_name)s : public %(base_class)s

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81 start_addr = 4;
82 break;
83 default:
84 panic("Unhandled Load/Store Multiple Instruction, "
85 "puswl = 0x%x", (unsigned) puswl);
86 break;
87 }
88
84// Macro Memory-format instructions
85//
86
87def template MacroStoreDeclare {{
88/**
89 * Static instructions class for a store multiple instruction
90 */
91class %(class_name)s : public %(base_class)s

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132 start_addr = 4;
133 break;
134 default:
135 panic("Unhandled Load/Store Multiple Instruction, "
136 "puswl = 0x%x", (unsigned) puswl);
137 break;
138 }
139
89 uint32_t newMachInst = 0;
90 newMachInst = machInst & 0xffff0000;
91 microOps[0] = new Addi_uop(newMachInst);
140 // Add 0 to Rn and stick it in Raddr (register 17).
141 // This is equivalent to a move.
142 microOps[0] = new MicroAddiUop(machInst, 17, RN, 0);
92
93 unsigned j = 0;
143
144 unsigned j = 0;
94 for (int i = 1; i < ones+1; i++)
95 {
145 for (int i = 1; i < ones+1; i++) {
96 // Get next available bit for transfer
97 while (! ( regs_to_handle & (1<<j)))
98 j++;
99 regs_to_handle &= ~(1<<j);
100
101 microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr);
102
103 if (up)
104 start_addr += 4;
105 else
106 start_addr -= 4;
107 }
108
146 // Get next available bit for transfer
147 while (! ( regs_to_handle & (1<<j)))
148 j++;
149 regs_to_handle &= ~(1<<j);
150
151 microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr);
152
153 if (up)
154 start_addr += 4;
155 else
156 start_addr -= 4;
157 }
158
109 if (writeback)
110 {
111 uint32_t newMachInst = machInst & 0xf0000000;
112 uint32_t rn = (machInst >> 16) & 0x0f;
113 // 3322 2222 2222 1111 1111 11
114 // 1098 7654 3210 9876 5432 1098 7654 3210
115 // COND 0010 0100 [RN] [RD] 0000 [ IMM ]
116 // sub rn, rn, imm
117 newMachInst |= 0x02400000;
118 newMachInst |= ((rn << 16) | (rn << 12));
119 newMachInst |= (ones << 2);
120 if (up)
121 {
122 microOps[numMicroops-1] = new Addi_rd_uop(newMachInst);
159 if (writeback) {
160 if (up) {
161 microOps[numMicroops-1] =
162 new MicroAddiUop(machInst, RN, RN, ones * 4);
163 } else {
164 microOps[numMicroops-1] =
165 new MicroSubiUop(machInst, RN, RN, ones * 4);
123 }
166 }
124 else
125 {
126 microOps[numMicroops-1] = new Subi_rd_uop(newMachInst);
127 }
128 }
129 microOps[numMicroops-1]->setLastMicroop();
130}
131
132}};
133
134def template MacroStoreExecute {{
135Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const

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161 start_addr = disp8;
162 else
163 start_addr = 0;
164
165 emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr);
166
167 if (writeback)
168 {
167 }
168 microOps[numMicroops-1]->setLastMicroop();
169}
170
171}};
172
173def template MacroStoreExecute {{
174Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const

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200 start_addr = disp8;
201 else
202 start_addr = 0;
203
204 emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr);
205
206 if (writeback)
207 {
169 uint32_t newMachInst = machInst & 0xf0000000;
170 uint32_t rn = (machInst >> 16) & 0x0f;
171 // 3322 2222 2222 1111 1111 11
172 // 1098 7654 3210 9876 5432 1098 7654 3210
173 // COND 0010 0100 [RN] [RD] 0000 [ IMM ]
174 // sub rn, rn, imm
175 newMachInst |= 0x02400000;
176 newMachInst |= ((rn << 16) | (rn << 12));
177 if (up)
178 {
179 newMachInst |= disp8;
180 microOps[numMicroops-1] = new Addi_rd_uop(newMachInst);
208 if (up) {
209 microOps[numMicroops-1] =
210 new MicroAddiUop(machInst, RN, RN, disp8);
211 } else {
212 microOps[numMicroops-1] =
213 new MicroSubiUop(machInst, RN, RN, disp8);
181 }
214 }
182 else
183 {
184 newMachInst |= disp8;
185 microOps[numMicroops-1] = new Subi_rd_uop(newMachInst);
186 }
187 }
188 microOps[numMicroops-1]->setLastMicroop();
189}
190
191}};
192
193
194def template MacroFMConstructor {{

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200 uint32_t start_addr = 0;
201
202 if (prepost)
203 start_addr = disp8;
204 else
205 start_addr = 0;
206
207 for (int i = 0; i < count; i++)
215 }
216 microOps[numMicroops-1]->setLastMicroop();
217}
218
219}};
220
221
222def template MacroFMConstructor {{

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228 uint32_t start_addr = 0;
229
230 if (prepost)
231 start_addr = disp8;
232 else
233 start_addr = 0;
234
235 for (int i = 0; i < count; i++)
208 {
209 emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr);
236 emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr);
210 }
211
237
212 if (writeback)
213 {
214 uint32_t newMachInst = machInst & 0xf0000000;
215 uint32_t rn = (machInst >> 16) & 0x0f;
216 // 3322 2222 2222 1111 1111 11
217 // 1098 7654 3210 9876 5432 1098 7654 3210
218 // COND 0010 0100 [RN] [RD] 0000 [ IMM ]
219 // sub rn, rn, imm
220 newMachInst |= 0x02400000;
221 newMachInst |= ((rn << 16) | (rn << 12));
222 if (up)
223 {
224 newMachInst |= disp8;
225 microOps[numMicroops-1] = new Addi_rd_uop(newMachInst);
238 if (writeback) {
239 if (up) {
240 microOps[numMicroops-1] =
241 new MicroAddiUop(machInst, RN, RN, disp8);
242 } else {
243 microOps[numMicroops-1] =
244 new MicroSubiUop(machInst, RN, RN, disp8);
226 }
245 }
227 else
228 {
229 newMachInst |= disp8;
230 microOps[numMicroops-1] = new Subi_rd_uop(newMachInst);
231 }
232 }
233 microOps[numMicroops-1]->setLastMicroop();
234}
235}};
236
237
238def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
239 iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)

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247 microOps[numMicroops-1]->setLastMicroop();
248}
249}};
250
251
252def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
253 iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)

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