macromem.isa (6258:dadfc8d8b6dd) macromem.isa (6304:a2af27fbc06c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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47}};
48
49def template MacroStoreConstructor {{
50inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
51 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
52{
53 %(constructor)s;
54 uint32_t regs_to_handle = reglist;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 38 unchanged lines hidden (view full) ---

47}};
48
49def template MacroStoreConstructor {{
50inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
51 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
52{
53 %(constructor)s;
54 uint32_t regs_to_handle = reglist;
55 uint32_t j = 0,
56 start_addr = 0,
57 end_addr = 0;
55 uint32_t start_addr = 0;
58
59 switch (puswl)
60 {
61 case 0x00: // stmda
62 case 0x01: // L ldmda_l
63 case 0x02: // W stmda_w
64 case 0x03: // WL ldmda_wl
65 start_addr = (ones << 2) - 4;
56
57 switch (puswl)
58 {
59 case 0x00: // stmda
60 case 0x01: // L ldmda_l
61 case 0x02: // W stmda_w
62 case 0x03: // WL ldmda_wl
63 start_addr = (ones << 2) - 4;
66 end_addr = 0;
67 break;
68 case 0x08: // U stmia_u
69 case 0x09: // U L ldmia_ul
70 case 0x0a: // U W stmia
71 case 0x0b: // U WL ldmia
72 start_addr = 0;
64 break;
65 case 0x08: // U stmia_u
66 case 0x09: // U L ldmia_ul
67 case 0x0a: // U W stmia
68 case 0x0b: // U WL ldmia
69 start_addr = 0;
73 end_addr = (ones << 2) - 4;
74 break;
75 case 0x10: // P stmdb
76 case 0x11: // P L ldmdb
77 case 0x12: // P W stmdb
78 case 0x13: // P WL ldmdb
79 start_addr = (ones << 2); // U-bit is already 0 for subtract
70 break;
71 case 0x10: // P stmdb
72 case 0x11: // P L ldmdb
73 case 0x12: // P W stmdb
74 case 0x13: // P WL ldmdb
75 start_addr = (ones << 2); // U-bit is already 0 for subtract
80 end_addr = 4; // negative 4
81 break;
82 case 0x18: // PU stmib
83 case 0x19: // PU L ldmib
84 case 0x1a: // PU W stmib
85 case 0x1b: // PU WL ldmib
86 start_addr = 4;
76 break;
77 case 0x18: // PU stmib
78 case 0x19: // PU L ldmib
79 case 0x1a: // PU W stmib
80 case 0x1b: // PU WL ldmib
81 start_addr = 4;
87 end_addr = (ones << 2) + 4;
88 break;
89 default:
90 panic("Unhandled Load/Store Multiple Instruction, "
91 "puswl = 0x%x", (unsigned) puswl);
92 break;
93 }
94
82 break;
83 default:
84 panic("Unhandled Load/Store Multiple Instruction, "
85 "puswl = 0x%x", (unsigned) puswl);
86 break;
87 }
88
95 //TODO - Add addi_uop/subi_uop here to create starting addresses
96 //Just using addi with 0 offset makes a "copy" of Rn for our use
97 uint32_t newMachInst = 0;
98 newMachInst = machInst & 0xffff0000;
99 microOps[0] = new Addi_uop(newMachInst);
100
89 uint32_t newMachInst = 0;
90 newMachInst = machInst & 0xffff0000;
91 microOps[0] = new Addi_uop(newMachInst);
92
93 unsigned j = 0;
101 for (int i = 1; i < ones+1; i++)
102 {
103 // Get next available bit for transfer
104 while (! ( regs_to_handle & (1<<j)))
105 j++;
106 regs_to_handle &= ~(1<<j);
107
108 microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr);
109
110 if (up)
111 start_addr += 4;
112 else
113 start_addr -= 4;
114 }
115
94 for (int i = 1; i < ones+1; i++)
95 {
96 // Get next available bit for transfer
97 while (! ( regs_to_handle & (1<<j)))
98 j++;
99 regs_to_handle &= ~(1<<j);
100
101 microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr);
102
103 if (up)
104 start_addr += 4;
105 else
106 start_addr -= 4;
107 }
108
116 /* TODO: Take a look at how these 2 values should meet together
117 if (start_addr != (end_addr - 4))
118 {
119 fprintf(stderr, "start_addr: %d\n", start_addr);
120 fprintf(stderr, "end_addr: %d\n", end_addr);
121 panic("start_addr does not meet end_addr");
122 }
123 */
124
125 if (writeback)
126 {
127 uint32_t newMachInst = machInst & 0xf0000000;
128 uint32_t rn = (machInst >> 16) & 0x0f;
129 // 3322 2222 2222 1111 1111 11
130 // 1098 7654 3210 9876 5432 1098 7654 3210
131 // COND 0010 0100 [RN] [RD] 0000 [ IMM ]
132 // sub rn, rn, imm

--- 150 unchanged lines hidden --- 		109 if (writeback)
110 {
111 uint32_t newMachInst = machInst & 0xf0000000;
112 uint32_t rn = (machInst >> 16) & 0x0f;
113 // 3322 2222 2222 1111 1111 11
114 // 1098 7654 3210 9876 5432 1098 7654 3210
115 // COND 0010 0100 [RN] [RD] 0000 [ IMM ]
116 // sub rn, rn, imm

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