macromem.isa (6253:988a001820f8) macromem.isa (6258:dadfc8d8b6dd)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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53 %(constructor)s;
54 uint32_t regs_to_handle = reglist;
55 uint32_t j = 0,
56 start_addr = 0,
57 end_addr = 0;
58
59 switch (puswl)
60 {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 44 unchanged lines hidden (view full) ---

53 %(constructor)s;
54 uint32_t regs_to_handle = reglist;
55 uint32_t j = 0,
56 start_addr = 0,
57 end_addr = 0;
58
59 switch (puswl)
60 {
61 case 0x00: // stmda
61 case 0x01: // L ldmda_l
62 case 0x01: // L ldmda_l
62 start_addr = (ones << 2) - 4;
63 end_addr = 0;
64 break;
63 case 0x02: // W stmda_w
65 case 0x03: // WL ldmda_wl
66 start_addr = (ones << 2) - 4;
67 end_addr = 0;
68 break;
69 case 0x08: // U stmia_u
64 case 0x03: // WL ldmda_wl
65 start_addr = (ones << 2) - 4;
66 end_addr = 0;
67 break;
68 case 0x08: // U stmia_u
70 start_addr = 0;
71 end_addr = (ones << 2) - 4;
72 break;
73 case 0x09: // U L ldmia_ul
69 case 0x09: // U L ldmia_ul
74 start_addr = 0;
75 end_addr = (ones << 2) - 4;
76 break;
70 case 0x0a: // U W stmia
77 case 0x0b: // U WL ldmia
78 start_addr = 0;
79 end_addr = (ones << 2) - 4;
80 break;
71 case 0x0b: // U WL ldmia
72 start_addr = 0;
73 end_addr = (ones << 2) - 4;
74 break;
75 case 0x10: // P stmdb
81 case 0x11: // P L ldmdb
76 case 0x11: // P L ldmdb
82 start_addr = (ones << 2); // U-bit is already 0 for subtract
83 end_addr = 4; // negative 4
84 break;
85 case 0x12: // P W stmdb
77 case 0x12: // P W stmdb
78 case 0x13: // P WL ldmdb
86 start_addr = (ones << 2); // U-bit is already 0 for subtract
87 end_addr = 4; // negative 4
88 break;
89 case 0x18: // PU stmib
79 start_addr = (ones << 2); // U-bit is already 0 for subtract
80 end_addr = 4; // negative 4
81 break;
82 case 0x18: // PU stmib
90 start_addr = 4;
91 end_addr = (ones << 2) + 4;
92 break;
93 case 0x19: // PU L ldmib
83 case 0x19: // PU L ldmib
84 case 0x1a: // PU W stmib
85 case 0x1b: // PU WL ldmib
94 start_addr = 4;
95 end_addr = (ones << 2) + 4;
96 break;
97 default:
86 start_addr = 4;
87 end_addr = (ones << 2) + 4;
88 break;
89 default:
98 panic("Unhandled Load/Store Multiple Instruction");
90 panic("Unhandled Load/Store Multiple Instruction, "
91 "puswl = 0x%x", (unsigned) puswl);
99 break;
100 }
101
102 //TODO - Add addi_uop/subi_uop here to create starting addresses
103 //Just using addi with 0 offset makes a "copy" of Rn for our use
104 uint32_t newMachInst = 0;
105 newMachInst = machInst & 0xffff0000;
106 microOps[0] = new Addi_uop(newMachInst);

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93 }
94
95 //TODO - Add addi_uop/subi_uop here to create starting addresses
96 //Just using addi with 0 offset makes a "copy" of Rn for our use
97 uint32_t newMachInst = 0;
98 newMachInst = machInst & 0xffff0000;
99 microOps[0] = new Addi_uop(newMachInst);

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