60a61
> case 0x00: // stmda
62,64c63
< start_addr = (ones << 2) - 4;
< end_addr = 0;
< break;
---
> case 0x02: // W stmda_w
70,72d68
< start_addr = 0;
< end_addr = (ones << 2) - 4;
< break;
74,76c70
< start_addr = 0;
< end_addr = (ones << 2) - 4;
< break;
---
> case 0x0a: // U W stmia
80a75
> case 0x10: // P stmdb
82,84d76
< start_addr = (ones << 2); // U-bit is already 0 for subtract
< end_addr = 4; // negative 4
< break;
85a78
> case 0x13: // P WL ldmdb
90,92d82
< start_addr = 4;
< end_addr = (ones << 2) + 4;
< break;
93a84,85
> case 0x1a: // PU W stmib
> case 0x1b: // PU WL ldmib
98c90,91
< panic("Unhandled Load/Store Multiple Instruction");
---
> panic("Unhandled Load/Store Multiple Instruction, "
> "puswl = 0x%x", (unsigned) puswl);