m5ops.isa (8734:79592b2b1d55) m5ops.isa (8782:10c9297e14d5)
1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 28 unchanged lines hidden (view full) ---

37// Authors: Gene Wu
38///
39
40def format M5ops() {{
41 decode_block = '''
42 {
43 const uint32_t m5func = bits(machInst, 23, 16);
44 switch(m5func) {
1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 28 unchanged lines hidden (view full) ---

37// Authors: Gene Wu
38///
39
40def format M5ops() {{
41 decode_block = '''
42 {
43 const uint32_t m5func = bits(machInst, 23, 16);
44 switch(m5func) {
45#if FULL_SYSTEM
46 case 0x00: return new Arm(machInst);
47 case 0x01: return new Quiesce(machInst);
48 case 0x02: return new QuiesceNs(machInst);
49 case 0x03: return new QuiesceCycles(machInst);
50 case 0x04: return new QuiesceTime(machInst);
45 case 0x00: return new Arm(machInst);
46 case 0x01: return new Quiesce(machInst);
47 case 0x02: return new QuiesceNs(machInst);
48 case 0x03: return new QuiesceCycles(machInst);
49 case 0x04: return new QuiesceTime(machInst);
51#endif
52 case 0x07: return new Rpns(machInst);
53 case 0x09: return new WakeCPU(machInst);
54 case 0x10: return new Deprecated_ivlb(machInst);
55 case 0x11: return new Deprecated_ivle(machInst);
56 case 0x20: return new Deprecated_exit (machInst);
57 case 0x21: return new M5exit(machInst);
50 case 0x07: return new Rpns(machInst);
51 case 0x09: return new WakeCPU(machInst);
52 case 0x10: return new Deprecated_ivlb(machInst);
53 case 0x11: return new Deprecated_ivle(machInst);
54 case 0x20: return new Deprecated_exit (machInst);
55 case 0x21: return new M5exit(machInst);
58#if FULL_SYSTEM
59 case 0x31: return new Loadsymbol(machInst);
60 case 0x30: return new Initparam(machInst);
56 case 0x31: return new Loadsymbol(machInst);
57 case 0x30: return new Initparam(machInst);
61#endif
62 case 0x40: return new Resetstats(machInst);
63 case 0x41: return new Dumpstats(machInst);
64 case 0x42: return new Dumpresetstats(machInst);
65 case 0x43: return new M5checkpoint(machInst);
58 case 0x40: return new Resetstats(machInst);
59 case 0x41: return new Dumpstats(machInst);
60 case 0x42: return new Dumpresetstats(machInst);
61 case 0x43: return new M5checkpoint(machInst);
66#if FULL_SYSTEM
67 case 0x4F: return new M5writefile(machInst);
68 case 0x50: return new M5readfile(machInst);
62 case 0x50: return new M5readfile(machInst);
69#endif
70 case 0x51: return new M5break(machInst);
71 case 0x52: return new M5switchcpu(machInst);
63 case 0x51: return new M5break(machInst);
64 case 0x52: return new M5switchcpu(machInst);
72#if FULL_SYSTEM
73 case 0x53: return new M5addsymbol(machInst);
65 case 0x53: return new M5addsymbol(machInst);
74#endif
75 case 0x54: return new M5panic(machInst);
76 case 0x5a: return new M5workbegin(machInst);
77 case 0x5b: return new M5workend(machInst);
78 }
79 }
80 '''
81}};
66 case 0x54: return new M5panic(machInst);
67 case 0x5a: return new M5workbegin(machInst);
68 case 0x5b: return new M5workend(machInst);
69 }
70 }
71 '''
72}};