fp.isa (9550:e0e2c8f83d08) fp.isa (10037:5cac77888310)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
3// Copyright (c) 2010-2011 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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146 uint32_t align = TLB::MustBeOne;
147 unsigned inc = 1;
148 unsigned regs = 1;
149 unsigned lane = 0;
150 if (single) {
151 if (singleAll) {
152 size = bits(machInst, 7, 6);
153 bool t = bits(machInst, 5);
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 134 unchanged lines hidden (view full) ---

146 uint32_t align = TLB::MustBeOne;
147 unsigned inc = 1;
148 unsigned regs = 1;
149 unsigned lane = 0;
150 if (single) {
151 if (singleAll) {
152 size = bits(machInst, 7, 6);
153 bool t = bits(machInst, 5);
154 unsigned eBytes = (1 << size);
155 align = (eBytes - 1) | TLB::AllowUnaligned;
154 align = size | TLB::AllowUnaligned;
156 if (width == 1) {
157 regs = t ? 2 : 1;
158 inc = 1;
159 } else {
160 regs = width;
161 inc = t ? 2 : 1;
162 }
163 switch (width) {
164 case 1:
165 case 2:
166 if (bits(machInst, 4))
155 if (width == 1) {
156 regs = t ? 2 : 1;
157 inc = 1;
158 } else {
159 regs = width;
160 inc = t ? 2 : 1;
161 }
162 switch (width) {
163 case 1:
164 case 2:
165 if (bits(machInst, 4))
167 align = width * eBytes - 1;
166 align = size + width - 1;
168 break;
169 case 3:
170 break;
171 case 4:
172 if (size == 3) {
173 if (bits(machInst, 4) == 0)
174 return new Unknown(machInst);
175 size = 2;
167 break;
168 case 3:
169 break;
170 case 4:
171 if (size == 3) {
172 if (bits(machInst, 4) == 0)
173 return new Unknown(machInst);
174 size = 2;
176 align = 0xf;
175 align = 0x4;
177 } else if (size == 2) {
178 if (bits(machInst, 4))
176 } else if (size == 2) {
177 if (bits(machInst, 4))
179 align = 7;
178 align = 0x3;
180 } else {
181 if (bits(machInst, 4))
179 } else {
180 if (bits(machInst, 4))
182 align = 4 * eBytes - 1;
181 align = size + 2;
183 }
184 break;
185 }
186 } else {
187 size = bits(machInst, 11, 10);
182 }
183 break;
184 }
185 } else {
186 size = bits(machInst, 11, 10);
188 unsigned eBytes = (1 << size);
189 align = (eBytes - 1) | TLB::AllowUnaligned;
187 align = size | TLB::AllowUnaligned;
190 regs = width;
191 unsigned indexAlign = bits(machInst, 7, 4);
192 // If width is 1, inc is always 1. That's overridden later.
193 switch (size) {
194 case 0:
195 inc = 1;
196 lane = bits(indexAlign, 3, 1);
197 break;

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214 case 0:
215 break;
216 case 1:
217 if (bits(indexAlign, 0))
218 align = 1;
219 break;
220 case 2:
221 if (bits(indexAlign, 1, 0))
188 regs = width;
189 unsigned indexAlign = bits(machInst, 7, 4);
190 // If width is 1, inc is always 1. That's overridden later.
191 switch (size) {
192 case 0:
193 inc = 1;
194 lane = bits(indexAlign, 3, 1);
195 break;

--- 16 unchanged lines hidden (view full) ---

212 case 0:
213 break;
214 case 1:
215 if (bits(indexAlign, 0))
216 align = 1;
217 break;
218 case 2:
219 if (bits(indexAlign, 1, 0))
222 align = 3;
220 align = 2;
223 break;
224 }
225 break;
226 case 2:
227 if (bits(indexAlign, 0))
221 break;
222 }
223 break;
224 case 2:
225 if (bits(indexAlign, 0))
228 align = (2 * eBytes) - 1;
226 align = size + 1;
229 break;
230 case 3:
231 break;
232 case 4:
233 switch (size) {
234 case 0:
235 case 1:
236 if (bits(indexAlign, 0))
227 break;
228 case 3:
229 break;
230 case 4:
231 switch (size) {
232 case 0:
233 case 1:
234 if (bits(indexAlign, 0))
237 align = (4 * eBytes) - 1;
235 align = size + 2;
238 break;
239 case 2:
240 if (bits(indexAlign, 0))
236 break;
237 case 2:
238 if (bits(indexAlign, 0))
241 align = (4 << bits(indexAlign, 1, 0)) - 1;
239 align = bits(indexAlign, 1, 0) + 2;
242 break;
243 }
244 break;
245 }
246 }
247 if (size == 0x3) {
248 return new Unknown(machInst);
249 }
250 } else {
251 size = bits(machInst, 7, 6);
252 align = bits(machInst, 5, 4);
253 if (align == 0) {
254 // @align wasn't specified, so alignment can be turned off.
240 break;
241 }
242 break;
243 }
244 }
245 if (size == 0x3) {
246 return new Unknown(machInst);
247 }
248 } else {
249 size = bits(machInst, 7, 6);
250 align = bits(machInst, 5, 4);
251 if (align == 0) {
252 // @align wasn't specified, so alignment can be turned off.
255 align = ((1 << size) - 1) | TLB::AllowUnaligned;
253 align = size | TLB::AllowUnaligned;
256 } else {
254 } else {
257 align = ((4 << align) - 1);
255 align = align + 2;
258 }
259 switch (width) {
260 case 1:
261 switch (type) {
262 case 0x7: regs = 1;
263 break;
264 case 0xa: regs = 2;
265 break;

--- 317 unchanged lines hidden (view full) ---

583 return decodeNeonSThreeSReg<VqrdmulhD, VqrdmulhQ>(
584 q, size, machInst, vd, vn, vm);
585 } else {
586 return decodeNeonSThreeSReg<VqdmulhD, VqdmulhQ>(
587 q, size, machInst, vd, vn, vm);
588 }
589 }
590 case 0xc:
256 }
257 switch (width) {
258 case 1:
259 switch (type) {
260 case 0x7: regs = 1;
261 break;
262 case 0xa: regs = 2;
263 break;

--- 317 unchanged lines hidden (view full) ---

581 return decodeNeonSThreeSReg<VqrdmulhD, VqrdmulhQ>(
582 q, size, machInst, vd, vn, vm);
583 } else {
584 return decodeNeonSThreeSReg<VqdmulhD, VqdmulhQ>(
585 q, size, machInst, vd, vn, vm);
586 }
587 }
588 case 0xc:
589 if (b) {
590 if (!u) {
591 if (bits(c, 1) == 0) {
592 if (q) {
593 return new NVfmaQFp<float>(machInst, vd, vn, vm);
594 } else {
595 return new NVfmaDFp<float>(machInst, vd, vn, vm);
596 }
597 } else {
598 if (q) {
599 return new NVfmsQFp<float>(machInst, vd, vn, vm);
600 } else {
601 return new NVfmsDFp<float>(machInst, vd, vn, vm);
602 }
603 }
604 }
605 }
591 return new Unknown(machInst);
592 case 0xd:
593 if (b) {
594 if (u) {
595 if (bits(c, 1) == 0) {
596 if (q) {
597 return new NVmulQFp<float>(machInst, vd, vn, vm);
598 } else {

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1822 } else {
1823 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
1824 rt, rt2);
1825 }
1826 }
1827 break;
1828 case 0x1:
1829 {
606 return new Unknown(machInst);
607 case 0xd:
608 if (b) {
609 if (u) {
610 if (bits(c, 1) == 0) {
611 if (q) {
612 return new NVmulQFp<float>(machInst, vd, vn, vm);
613 } else {

--- 1223 unchanged lines hidden (view full) ---

1837 } else {
1838 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
1839 rt, rt2);
1840 }
1841 }
1842 break;
1843 case 0x1:
1844 {
1830 if (offset == 0 || vd + offset/2 > NumFloatArchRegs) {
1845 if (offset == 0 || vd + offset/2 > NumFloatV7ArchRegs) {
1831 break;
1832 }
1833 switch (bits(opcode, 1, 0)) {
1834 case 0x0:
1835 return new VLdmStm(machInst, rn, vd, single,
1836 true, false, false, offset);
1837 case 0x1:
1838 return new VLdmStm(machInst, rn, vd, single,

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1946 if (bits(machInst, 20) == 1) {
1947 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
1948 } else {
1949 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
1950 }
1951 } else if (a == 0x7) {
1952 const IntRegIndex rt =
1953 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
1846 break;
1847 }
1848 switch (bits(opcode, 1, 0)) {
1849 case 0x0:
1850 return new VLdmStm(machInst, rn, vd, single,
1851 true, false, false, offset);
1852 case 0x1:
1853 return new VLdmStm(machInst, rn, vd, single,

--- 107 unchanged lines hidden (view full) ---

1961 if (bits(machInst, 20) == 1) {
1962 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
1963 } else {
1964 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
1965 }
1966 } else if (a == 0x7) {
1967 const IntRegIndex rt =
1968 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
1954 uint32_t specReg = bits(machInst, 19, 16);
1955 switch (specReg) {
1969 uint32_t reg = bits(machInst, 19, 16);
1970 uint32_t specReg;
1971 switch (reg) {
1956 case 0:
1957 specReg = MISCREG_FPSID;
1958 break;
1959 case 1:
1960 specReg = MISCREG_FPSCR;
1961 break;
1962 case 6:
1963 specReg = MISCREG_MVFR1;

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1969 specReg = MISCREG_FPEXC;
1970 break;
1971 default:
1972 return new Unknown(machInst);
1973 }
1974 if (specReg == MISCREG_FPSCR) {
1975 return new VmsrFpscr(machInst, (IntRegIndex)specReg, rt);
1976 } else {
1972 case 0:
1973 specReg = MISCREG_FPSID;
1974 break;
1975 case 1:
1976 specReg = MISCREG_FPSCR;
1977 break;
1978 case 6:
1979 specReg = MISCREG_MVFR1;

--- 5 unchanged lines hidden (view full) ---

1985 specReg = MISCREG_FPEXC;
1986 break;
1987 default:
1988 return new Unknown(machInst);
1989 }
1990 if (specReg == MISCREG_FPSCR) {
1991 return new VmsrFpscr(machInst, (IntRegIndex)specReg, rt);
1992 } else {
1977 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
1993 uint32_t iss = mcrMrcIssBuild(0, bits(machInst, 3, 0), rt,
1994 reg, a, bits(machInst, 7, 5));
1995 return new Vmsr(machInst, (IntRegIndex)specReg, rt, iss);
1978 }
1979 }
1980 } else if (l == 0 && c == 1) {
1981 if (bits(a, 2) == 0) {
1982 uint32_t vd = (bits(machInst, 7) << 5) |
1983 (bits(machInst, 19, 16) << 1);
1984 // Handle accessing each single precision half of the vector.
1985 vd += bits(machInst, 21);

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2036 if (bits(machInst, 20) == 1) {
2037 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
2038 } else {
2039 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
2040 }
2041 } else if (a == 7) {
2042 const IntRegIndex rt =
2043 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
1996 }
1997 }
1998 } else if (l == 0 && c == 1) {
1999 if (bits(a, 2) == 0) {
2000 uint32_t vd = (bits(machInst, 7) << 5) |
2001 (bits(machInst, 19, 16) << 1);
2002 // Handle accessing each single precision half of the vector.
2003 vd += bits(machInst, 21);

--- 50 unchanged lines hidden (view full) ---

2054 if (bits(machInst, 20) == 1) {
2055 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
2056 } else {
2057 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
2058 }
2059 } else if (a == 7) {
2060 const IntRegIndex rt =
2061 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
2044 uint32_t specReg = bits(machInst, 19, 16);
2045 switch (specReg) {
2062 uint32_t reg = bits(machInst, 19, 16);
2063 uint32_t specReg;
2064 switch (reg) {
2046 case 0:
2047 specReg = MISCREG_FPSID;
2048 break;
2049 case 1:
2050 specReg = MISCREG_FPSCR;
2051 break;
2052 case 6:
2053 specReg = MISCREG_MVFR1;

--- 11 unchanged lines hidden (view full) ---

2065 if (specReg == MISCREG_FPSCR) {
2066 return new VmrsApsrFpscr(machInst);
2067 } else {
2068 return new Unknown(machInst);
2069 }
2070 } else if (specReg == MISCREG_FPSCR) {
2071 return new VmrsFpscr(machInst, rt, (IntRegIndex)specReg);
2072 } else {
2065 case 0:
2066 specReg = MISCREG_FPSID;
2067 break;
2068 case 1:
2069 specReg = MISCREG_FPSCR;
2070 break;
2071 case 6:
2072 specReg = MISCREG_MVFR1;

--- 11 unchanged lines hidden (view full) ---

2084 if (specReg == MISCREG_FPSCR) {
2085 return new VmrsApsrFpscr(machInst);
2086 } else {
2087 return new Unknown(machInst);
2088 }
2089 } else if (specReg == MISCREG_FPSCR) {
2090 return new VmrsFpscr(machInst, rt, (IntRegIndex)specReg);
2091 } else {
2073 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
2092 uint32_t iss = mcrMrcIssBuild(l, bits(machInst, 3, 0), rt,
2093 reg, a, bits(machInst, 7, 5));
2094 return new Vmrs(machInst, rt, (IntRegIndex)specReg, iss);
2074 }
2075 }
2076 } else {
2077 uint32_t vd = (bits(machInst, 7) << 5) |
2078 (bits(machInst, 19, 16) << 1);
2079 // Handle indexing into each single precision half of the vector.
2080 vd += bits(machInst, 21);
2081 uint32_t index;

--- 148 unchanged lines hidden (view full) ---

2230 return decodeVfpRegRegRegOp<VdivS>(
2231 machInst, vd, vn, vm, false);
2232 } else {
2233 return decodeVfpRegRegRegOp<VdivD>(
2234 machInst, vd, vn, vm, true);
2235 }
2236 }
2237 break;
2095 }
2096 }
2097 } else {
2098 uint32_t vd = (bits(machInst, 7) << 5) |
2099 (bits(machInst, 19, 16) << 1);
2100 // Handle indexing into each single precision half of the vector.
2101 vd += bits(machInst, 21);
2102 uint32_t index;

--- 148 unchanged lines hidden (view full) ---

2251 return decodeVfpRegRegRegOp<VdivS>(
2252 machInst, vd, vn, vm, false);
2253 } else {
2254 return decodeVfpRegRegRegOp<VdivD>(
2255 machInst, vd, vn, vm, true);
2256 }
2257 }
2258 break;
2259 case 0x9:
2260 if ((opc3 & 0x1) == 0) {
2261 if (single) {
2262 return decodeVfpRegRegRegOp<VfnmaS>(
2263 machInst, vd, vn, vm, false);
2264 } else {
2265 return decodeVfpRegRegRegOp<VfnmaD>(
2266 machInst, vd, vn, vm, true);
2267 }
2268 } else {
2269 if (single) {
2270 return decodeVfpRegRegRegOp<VfnmsS>(
2271 machInst, vd, vn, vm, false);
2272 } else {
2273 return decodeVfpRegRegRegOp<VfnmsD>(
2274 machInst, vd, vn, vm, true);
2275 }
2276 }
2277 break;
2278 case 0xa:
2279 if ((opc3 & 0x1) == 0) {
2280 if (single) {
2281 return decodeVfpRegRegRegOp<VfmaS>(
2282 machInst, vd, vn, vm, false);
2283 } else {
2284 return decodeVfpRegRegRegOp<VfmaD>(
2285 machInst, vd, vn, vm, true);
2286 }
2287 } else {
2288 if (single) {
2289 return decodeVfpRegRegRegOp<VfmsS>(
2290 machInst, vd, vn, vm, false);
2291 } else {
2292 return decodeVfpRegRegRegOp<VfmsD>(
2293 machInst, vd, vn, vm, true);
2294 }
2295 }
2296 break;
2238 case 0xb:
2239 if ((opc3 & 0x1) == 0) {
2240 const uint32_t baseImm =
2241 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
2242 if (single) {
2243 uint32_t imm = vfp_modified_imm(baseImm, false);
2244 return decodeVfpRegImmOp<VmovImmS>(
2245 machInst, vd, imm, false);

--- 254 unchanged lines hidden --- 		2297 case 0xb:
2298 if ((opc3 & 0x1) == 0) {
2299 const uint32_t baseImm =
2300 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
2301 if (single) {
2302 uint32_t imm = vfp_modified_imm(baseImm, false);
2303 return decodeVfpRegImmOp<VmovImmS>(
2304 machInst, vd, imm, false);

--- 254 unchanged lines hidden ---