fp.isa (7413:18e0f95d1f32) fp.isa (7435:62bdb68bb314)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48let {{
49 header_output = '''
50 StaticInstPtr
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 34 unchanged lines hidden (view full) ---

43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48let {{
49 header_output = '''
50 StaticInstPtr
51 decodeNeonMem(ExtMachInst machInst);
52
53 StaticInstPtr
54 decodeNeonData(ExtMachInst machInst);
55 '''
56
57 decoder_output = '''
58 StaticInstPtr
59 decodeNeonMem(ExtMachInst machInst)
60 {
61 const uint32_t b = bits(machInst, 11, 8);
62 const bool a = bits(machInst, 23);
63 const bool l = bits(machInst, 21);
64
65 if (l) {
66 // Load instructions.
67 if (a) {
68 switch (b) {
69 }
70 // Single.
71 } else {
72 switch (b) {
73 }
74 // Multiple.
75 }
76 } else {
77 // Store instructions.
78 if (a) {
79 switch (b) {
80 }
81 // Single.
82 } else {
83 switch (b) {
84 }
85 // Multiple.
86 }
87 }
88 return new WarnUnimplemented("neon memory", machInst);
89 }
90 '''
91
92 decoder_output += '''
93 static StaticInstPtr
94 decodeNeonThreeRegistersSameLength(ExtMachInst machInst)
95 {
96 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
97 const uint32_t a = bits(machInst, 11, 8);
98 const bool b = bits(machInst, 4);
99 const uint32_t c = bits(machInst, 21, 20);
100 switch (a) {
101 case 0x0:
102 if (b) {
103 if (bits(machInst, 9) == 0) {
104 return new WarnUnimplemented("vhadd", machInst);
105 } else {
106 return new WarnUnimplemented("vhsub", machInst);
107 }
108 } else {
109 return new WarnUnimplemented("vqadd", machInst);
110 }
111 case 0x1:
112 if (!b) {
113 return new WarnUnimplemented("vrhadd", machInst);
114 } else {
115 if (u) {
116 switch (c) {
117 case 0:
118 return new WarnUnimplemented("veor", machInst);
119 case 1:
120 return new WarnUnimplemented("vbsl", machInst);
121 case 2:
122 return new WarnUnimplemented("vbit", machInst);
123 case 3:
124 return new WarnUnimplemented("vbif", machInst);
125 }
126 } else {
127 switch (c) {
128 case 0:
129 return new WarnUnimplemented("vand (reg)", machInst);
130 case 1:
131 return new WarnUnimplemented("vbic (reg)", machInst);
132 case 2:
133 {
134 const IntRegIndex n = (IntRegIndex)(
135 (uint32_t)bits(machInst, 19, 16) |
136 (uint32_t)(bits(machInst, 7) << 4));
137 const IntRegIndex m = (IntRegIndex)(
138 (uint32_t)bits(machInst, 3, 0) |
139 (uint32_t)(bits(machInst, 5) << 4));
140 if (n == m) {
141 return new WarnUnimplemented("vmov (reg)",
142 machInst);
143 } else {
144 return new WarnUnimplemented("vorr (reg)",
145 machInst);
146 }
147 }
148 case 3:
149 return new WarnUnimplemented("vorn (reg)", machInst);
150 }
151 }
152 }
153 case 0x2:
154 if (b) {
155 return new WarnUnimplemented("vqsub", machInst);
156 } else {
157 if (bits(machInst, 9) == 0) {
158 return new WarnUnimplemented("vhadd", machInst);
159 } else {
160 return new WarnUnimplemented("vhsub", machInst);
161 }
162 }
163 case 0x3:
164 if (b) {
165 return new WarnUnimplemented("vcge (reg)", machInst);
166 } else {
167 return new WarnUnimplemented("vcgt (reg)", machInst);
168 }
169 case 0x4:
170 if (b) {
171 return new WarnUnimplemented("vqshl (reg)", machInst);
172 } else {
173 return new WarnUnimplemented("vshl (reg)", machInst);
174 }
175 case 0x5:
176 if (b) {
177 return new WarnUnimplemented("vqrshl", machInst);
178 } else {
179 return new WarnUnimplemented("vrshl", machInst);
180 }
181 case 0x6:
182 if (b) {
183 return new WarnUnimplemented("vmin (int)", machInst);
184 } else {
185 return new WarnUnimplemented("vmax (int)", machInst);
186 }
187 case 0x7:
188 if (b) {
189 return new WarnUnimplemented("vaba", machInst);
190 } else {
191 if (bits(machInst, 23) == 1) {
192 if (bits(machInst, 6) == 1) {
193 return new Unknown(machInst);
194 } else {
195 return new WarnUnimplemented("vabdl (int)", machInst);
196 }
197 } else {
198 return new WarnUnimplemented("vabd (int)", machInst);
199 }
200 }
201 case 0x8:
202 if (b) {
203 if (u) {
204 return new WarnUnimplemented("vceq (reg)", machInst);
205 } else {
206 return new WarnUnimplemented("vtst", machInst);
207 }
208 } else {
209 if (u) {
210 return new WarnUnimplemented("vsub (int)", machInst);
211 } else {
212 return new WarnUnimplemented("vadd (int)", machInst);
213 }
214 }
215 case 0x9:
216 if (b) {
217 if (u) {
218 return new WarnUnimplemented("vmul (poly)", machInst);
219 } else {
220 return new WarnUnimplemented("vmul (int)", machInst);
221 }
222 } else {
223 if (u) {
224 return new WarnUnimplemented("vmls (int)", machInst);
225 } else {
226 return new WarnUnimplemented("vmla (int)", machInst);
227 }
228 }
229 case 0xa:
230 if (b) {
231 return new WarnUnimplemented("vpmin (int)", machInst);
232 } else {
233 return new WarnUnimplemented("vpmax (int)", machInst);
234 }
235 case 0xb:
236 if (b) {
237 if (u) {
238 return new Unknown(machInst);
239 } else {
240 return new WarnUnimplemented("vpadd (int)", machInst);
241 }
242 } else {
243 if (u) {
244 return new WarnUnimplemented("vqrdmulh", machInst);
245 } else {
246 return new WarnUnimplemented("vqdmulh", machInst);
247 }
248 }
249 case 0xc:
250 return new Unknown(machInst);
251 case 0xd:
252 if (b) {
253 if (u) {
254 if (bits(c, 1) == 0) {
255 return new WarnUnimplemented("vmul (fp)", machInst);
256 } else {
257 return new Unknown(machInst);
258 }
259 } else {
260 if (bits(c, 1) == 0) {
261 return new WarnUnimplemented("vmla (fp)", machInst);
262 } else {
263 return new WarnUnimplemented("vmls (fp)", machInst);
264 }
265 }
266 } else {
267 if (u) {
268 if (bits(c, 1) == 0) {
269 return new WarnUnimplemented("vpadd (fp)", machInst);
270 } else {
271 return new WarnUnimplemented("vabd (fp)", machInst);
272 }
273 } else {
274 if (bits(c, 1) == 0) {
275 return new WarnUnimplemented("vadd (fp)", machInst);
276 } else {
277 return new WarnUnimplemented("vsub (fp)", machInst);
278 }
279 }
280 }
281 case 0xe:
282 if (b) {
283 if (u) {
284 if (bits(c, 1) == 0) {
285 return new WarnUnimplemented("vacge", machInst);
286 } else {
287 return new WarnUnimplemented("vacgt", machInst);
288 }
289 } else {
290 return new Unknown(machInst);
291 }
292 } else {
293 if (u) {
294 if (bits(c, 1) == 0) {
295 return new WarnUnimplemented("vcge (reg)", machInst);
296 } else {
297 return new WarnUnimplemented("vcgt (reg)", machInst);
298 }
299 } else {
300 if (bits(c, 1) == 0) {
301 return new WarnUnimplemented("vceq (reg)", machInst);
302 } else {
303 return new Unknown(machInst);
304 }
305 }
306 }
307 case 0xf:
308 if (b) {
309 if (u) {
310 return new Unknown(machInst);
311 } else {
312 if (bits(c, 1) == 0) {
313 return new WarnUnimplemented("vrecps", machInst);
314 } else {
315 return new WarnUnimplemented("vrsqrts", machInst);
316 }
317 }
318 } else {
319 if (u) {
320 if (bits(c, 1) == 0) {
321 return new WarnUnimplemented("vpmax (fp)", machInst);
322 } else {
323 return new WarnUnimplemented("vpmin (fp)", machInst);
324 }
325 } else {
326 if (bits(c, 1) == 0) {
327 return new WarnUnimplemented("vmax (fp)", machInst);
328 } else {
329 return new WarnUnimplemented("vmin (fp)", machInst);
330 }
331 }
332 }
333 }
334 return new Unknown(machInst);
335 }
336
337 static StaticInstPtr
338 decodeNeonOneRegModImm(ExtMachInst machInst)
339 {
340 const bool op = bits(machInst, 5);
341 const uint32_t cmode = bits(machInst, 11, 8);
342 if (op) {
343 if (bits(cmode, 3) == 0) {
344 if (bits(cmode, 0) == 0) {
345 return new WarnUnimplemented("vmov (imm)", machInst);
346 } else {
347 return new WarnUnimplemented("vorr (imm)", machInst);
348 }
349 } else {
350 if (bits(cmode, 2) == 1) {
351 return new WarnUnimplemented("vmov (imm)", machInst);
352 } else {
353 if (bits(cmode, 0) == 0) {
354 return new WarnUnimplemented("vmov (imm)", machInst);
355 } else {
356 return new WarnUnimplemented("vorr (imm)", machInst);
357 }
358 }
359 }
360 } else {
361 if (bits(cmode, 3) == 0) {
362 if (bits(cmode, 0) == 0) {
363 return new WarnUnimplemented("vmvn (imm)", machInst);
364 } else {
365 return new WarnUnimplemented("vbic (imm)", machInst);
366 }
367 } else {
368 if (bits(cmode, 2) == 1) {
369 switch (bits(cmode, 1, 0)) {
370 case 0:
371 case 1:
372 return new WarnUnimplemented("vmvn (imm)", machInst);
373 case 2:
374 return new WarnUnimplemented("vmov (imm)", machInst);
375 case 3:
376 return new Unknown(machInst);
377 }
378 return new WarnUnimplemented("vmov (imm)", machInst);
379 } else {
380 if (bits(cmode, 0) == 0) {
381 return new WarnUnimplemented("vmvn (imm)", machInst);
382 } else {
383 return new WarnUnimplemented("vbic (imm)", machInst);
384 }
385 }
386 }
387 }
388 return new Unknown(machInst);
389 }
390
391 static StaticInstPtr
392 decodeNeonTwoRegAndShift(ExtMachInst machInst)
393 {
394 const uint32_t a = bits(machInst, 11, 8);
395 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
396 const bool b = bits(machInst, 6);
397 const bool l = bits(machInst, 7);
398
399 switch (a) {
400 case 0x0:
401 return new WarnUnimplemented("vshr", machInst);
402 case 0x1:
403 return new WarnUnimplemented("vsra", machInst);
404 case 0x2:
405 return new WarnUnimplemented("vrshr", machInst);
406 case 0x3:
407 return new WarnUnimplemented("vrsra", machInst);
408 case 0x4:
409 if (u) {
410 return new WarnUnimplemented("vsri", machInst);
411 } else {
412 return new Unknown(machInst);
413 }
414 case 0x5:
415 if (u) {
416 return new WarnUnimplemented("vsli", machInst);
417 } else {
418 return new WarnUnimplemented("vshl (imm)", machInst);
419 }
420 case 0x6:
421 case 0x7:
422 return new WarnUnimplemented("vqshl, vqshlu (imm)", machInst);
423 case 0x8:
424 if (l) {
425 return new Unknown(machInst);
426 } else if (u) {
427 if (b) {
428 return new WarnUnimplemented("vqrshrn, vqrshrun", machInst);
429 } else {
430 return new WarnUnimplemented("vqshrn, vqshrun", machInst);
431 }
432 } else {
433 if (b) {
434 return new WarnUnimplemented("vrshrn", machInst);
435 } else {
436 return new WarnUnimplemented("vshrn", machInst);
437 }
438 }
439 case 0x9:
440 if (l) {
441 return new Unknown(machInst);
442 } else if (b) {
443 return new WarnUnimplemented("vqrshrn, vqrshrun", machInst);
444 } else {
445 return new WarnUnimplemented("vqshrn, vqshrun", machInst);
446 }
447 case 0xa:
448 if (l || b) {
449 return new Unknown(machInst);
450 } else {
451 // If the shift amount is zero, it's vmovl.
452 return new WarnUnimplemented("vshll, vmovl", machInst);
453 }
454 case 0xe:
455 case 0xf:
456 if (l) {
457 return new Unknown(machInst);
458 } else if (a == 0xe) {
459 return new WarnUnimplemented("vcvt (fixed to fp)", machInst);
460 } else if (a == 0xf) {
461 return new WarnUnimplemented("vcvt (fp to fixed)", machInst);
462 }
463 }
464 return new Unknown(machInst);
465 }
466
467 static StaticInstPtr
468 decodeNeonThreeRegDiffLengths(ExtMachInst machInst)
469 {
470 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
471 const uint32_t a = bits(machInst, 11, 8);
472
473 switch (a) {
474 case 0x0:
475 return new WarnUnimplemented("vaddl", machInst);
476 case 0x1:
477 return new WarnUnimplemented("vaddw", machInst);
478 case 0x2:
479 return new WarnUnimplemented("vsubl", machInst);
480 case 0x3:
481 return new WarnUnimplemented("vsubw", machInst);
482 case 0x4:
483 if (u) {
484 return new WarnUnimplemented("vraddhn", machInst);
485 } else {
486 return new WarnUnimplemented("vaddhn", machInst);
487 }
488 case 0x5:
489 return new WarnUnimplemented("vabal", machInst);
490 case 0x6:
491 if (u) {
492 return new WarnUnimplemented("vrsubhn", machInst);
493 } else {
494 return new WarnUnimplemented("vsubhn", machInst);
495 }
496 case 0x7:
497 if (bits(machInst, 23)) {
498 return new WarnUnimplemented("vabdl (int)", machInst);
499 } else {
500 return new WarnUnimplemented("vabd (int)", machInst);
501 }
502 case 0x8:
503 return new WarnUnimplemented("vmlal (int)", machInst);
504 case 0xa:
505 return new WarnUnimplemented("vmlsl (int)", machInst);
506 case 0x9:
507 if (bits(machInst, 23) == 0) {
508 if (bits(machInst, 4) == 0) {
509 if (u) {
510 return new WarnUnimplemented("vmls (int)", machInst);
511 } else {
512 return new WarnUnimplemented("vmla (int)", machInst);
513 }
514 } else {
515 if (u) {
516 return new WarnUnimplemented("vmul (poly)", machInst);
517 } else {
518 return new WarnUnimplemented("vmul (int)", machInst);
519 }
520 }
521 } else {
522 return new WarnUnimplemented("vqdmlal", machInst);
523 }
524 case 0xb:
525 if (!u) {
526 return new Unknown(machInst);
527 } else {
528 return new WarnUnimplemented("vqdmlsl", machInst);
529 }
530 case 0xc:
531 return new WarnUnimplemented("vmull (int)", machInst);
532 case 0xd:
533 if (!u) {
534 return new Unknown(machInst);
535 } else {
536 return new WarnUnimplemented("vqdmull", machInst);
537 }
538 case 0xe:
539 return new WarnUnimplemented("vmull (poly)", machInst);
540 }
541 return new Unknown(machInst);
542 }
543
544 static StaticInstPtr
545 decodeNeonTwoRegScalar(ExtMachInst machInst)
546 {
547 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
548 const uint32_t a = bits(machInst, 11, 8);
549
550 switch (a) {
551 case 0x0:
552 return new WarnUnimplemented("vmla (int scalar)", machInst);
553 case 0x1:
554 return new WarnUnimplemented("vmla (fp scalar)", machInst);
555 case 0x4:
556 return new WarnUnimplemented("vmls (int scalar)", machInst);
557 case 0x5:
558 return new WarnUnimplemented("vmls (fp scalar)", machInst);
559 case 0x2:
560 return new WarnUnimplemented("vmlal (scalar)", machInst);
561 case 0x6:
562 return new WarnUnimplemented("vmlsl (scalar)", machInst);
563 case 0x3:
564 if (u) {
565 return new Unknown(machInst);
566 } else {
567 return new WarnUnimplemented("vqdmlal", machInst);
568 }
569 case 0x7:
570 if (u) {
571 return new Unknown(machInst);
572 } else {
573 return new WarnUnimplemented("vqdmlsl", machInst);
574 }
575 case 0x8:
576 return new WarnUnimplemented("vmul (int scalar)", machInst);
577 case 0x9:
578 return new WarnUnimplemented("vmul (fp scalar)", machInst);
579 case 0xa:
580 return new WarnUnimplemented("vmull (scalar)", machInst);
581 case 0xb:
582 if (u) {
583 return new Unknown(machInst);
584 } else {
585 return new WarnUnimplemented("vqdmull", machInst);
586 }
587 case 0xc:
588 return new WarnUnimplemented("vqdmulh", machInst);
589 case 0xd:
590 return new WarnUnimplemented("vqrdmulh", machInst);
591 }
592 return new Unknown(machInst);
593 }
594
595 static StaticInstPtr
596 decodeNeonTwoRegMisc(ExtMachInst machInst)
597 {
598 const uint32_t a = bits(machInst, 17, 16);
599 const uint32_t b = bits(machInst, 10, 6);
600 switch (a) {
601 case 0x0:
602 switch (bits(b, 4, 1)) {
603 case 0x0:
604 return new WarnUnimplemented("vrev64", machInst);
605 case 0x1:
606 return new WarnUnimplemented("vrev32", machInst);
607 case 0x2:
608 return new WarnUnimplemented("vrev16", machInst);
609 case 0x4:
610 case 0x5:
611 return new WarnUnimplemented("vpaddl", machInst);
612 case 0x8:
613 return new WarnUnimplemented("vcls", machInst);
614 case 0x9:
615 return new WarnUnimplemented("vclz", machInst);
616 case 0xa:
617 return new WarnUnimplemented("vcnt", machInst);
618 case 0xb:
619 return new WarnUnimplemented("vmvn (reg)", machInst);
620 case 0xc:
621 case 0xd:
622 return new WarnUnimplemented("vpadal", machInst);
623 case 0xe:
624 return new WarnUnimplemented("vqabs", machInst);
625 case 0xf:
626 return new WarnUnimplemented("vqneg", machInst);
627 default:
628 return new Unknown(machInst);
629 }
630 case 0x1:
631 switch (bits(b, 3, 1)) {
632 case 0x0:
633 return new WarnUnimplemented("vcgt (imm #0)", machInst);
634 case 0x1:
635 return new WarnUnimplemented("vcge (imm #0)", machInst);
636 case 0x2:
637 return new WarnUnimplemented("vceq (imm #0)", machInst);
638 case 0x3:
639 return new WarnUnimplemented("vcle (imm #0)", machInst);
640 case 0x4:
641 return new WarnUnimplemented("vclt (imm #0)", machInst);
642 case 0x6:
643 return new WarnUnimplemented("vabs (imm #0)", machInst);
644 case 0x7:
645 return new WarnUnimplemented("vneg (imm #0)", machInst);
646 }
647 case 0x2:
648 switch (bits(b, 4, 1)) {
649 case 0x0:
650 return new WarnUnimplemented("vswp", machInst);
651 case 0x1:
652 return new WarnUnimplemented("vtrn", machInst);
653 case 0x2:
654 return new WarnUnimplemented("vuzp", machInst);
655 case 0x3:
656 return new WarnUnimplemented("vzip", machInst);
657 case 0x4:
658 if (b == 0x8) {
659 return new WarnUnimplemented("vmovn", machInst);
660 } else {
661 return new WarnUnimplemented("vqmovun", machInst);
662 }
663 case 0x5:
664 return new WarnUnimplemented("vqmovn", machInst);
665 case 0x6:
666 if (b == 0xc) {
667 return new WarnUnimplemented("vshll", machInst);
668 } else {
669 return new Unknown(machInst);
670 }
671 case 0xc:
672 case 0xe:
673 if (b == 0x18) {
674 return new WarnUnimplemented("vcvt (single to half)",
675 machInst);
676 } else if (b == 0x1c) {
677 return new WarnUnimplemented("vcvt (half to single)",
678 machInst);
679 } else {
680 return new Unknown(machInst);
681 }
682 default:
683 return new Unknown(machInst);
684 }
685 case 0x3:
686 if (bits(b, 4, 3) == 0x3) {
687 return new WarnUnimplemented("vcvt (fp and int)", machInst);
688 } else if ((b & 0x1a) == 0x10) {
689 return new WarnUnimplemented("vrecpe", machInst);
690 } else if ((b & 0x1a) == 0x12) {
691 return new WarnUnimplemented("vrsqrte", machInst);
692 } else {
693 return new Unknown(machInst);
694 }
695 }
696 return new Unknown(machInst);
697 }
698
699 StaticInstPtr
700 decodeNeonData(ExtMachInst machInst)
701 {
702 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
703 const uint32_t a = bits(machInst, 23, 19);
704 const uint32_t b = bits(machInst, 11, 8);
705 const uint32_t c = bits(machInst, 7, 4);
706 if (bits(a, 4) == 0) {
707 return decodeNeonThreeRegistersSameLength(machInst);
708 } else if ((c & 0x9) == 1) {
709 if ((a & 0x7) == 0) {
710 return decodeNeonOneRegModImm(machInst);
711 } else {
712 return decodeNeonTwoRegAndShift(machInst);
713 }
714 } else if ((c & 0x9) == 9) {
715 return decodeNeonTwoRegAndShift(machInst);
716 } else if ((c & 0x5) == 0) {
717 if (bits(a, 3, 2) != 0x3) {
718 return decodeNeonThreeRegDiffLengths(machInst);
719 }
720 } else if ((c & 0x5) == 4) {
721 if (bits(a, 3, 2) != 0x3) {
722 return decodeNeonTwoRegScalar(machInst);
723 }
724 } else if ((a & 0x16) == 0x16) {
725 if (!u) {
726 if (bits(c, 0) == 0) {
727 return new WarnUnimplemented("vext", machInst);
728 }
729 } else if (bits(b, 3) == 0 && bits(c, 0) == 0) {
730 return decodeNeonTwoRegMisc(machInst);
731 } else if (bits(b, 3, 2) == 0x2 && bits(c, 0) == 0) {
732 if (bits(machInst, 6) == 0) {
733 return new WarnUnimplemented("vtbl", machInst);
734 } else {
735 return new WarnUnimplemented("vtbx", machInst);
736 }
737 } else if (b == 0xc && (c & 0x9) == 0) {
738 return new WarnUnimplemented("vdup (scalar)", machInst);
739 }
740 }
741 return new Unknown(machInst);
742 }
743 '''
744}};
745
746def format ThumbNeonMem() {{
747 decode_block = '''
748 return decodeNeonMem(machInst);
749 '''
750}};
751
752def format ThumbNeonData() {{
753 decode_block = '''
754 return decodeNeonMem(machInst);
755 '''
756}};
757
758let {{
759 header_output = '''
760 StaticInstPtr
51 decodeExtensionRegLoadStore(ExtMachInst machInst);
52 '''
53 decoder_output = '''
54 StaticInstPtr
55 decodeExtensionRegLoadStore(ExtMachInst machInst)
56 {
57 const uint32_t opcode = bits(machInst, 24, 20);
58 const uint32_t offset = bits(machInst, 7, 0);

--- 710 unchanged lines hidden --- 		761 decodeExtensionRegLoadStore(ExtMachInst machInst);
762 '''
763 decoder_output = '''
764 StaticInstPtr
765 decodeExtensionRegLoadStore(ExtMachInst machInst)
766 {
767 const uint32_t opcode = bits(machInst, 24, 20);
768 const uint32_t offset = bits(machInst, 7, 0);

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