fp.isa (7394:bd00fbc41bb1) fp.isa (7398:063002e7106b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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650 machInst, vd, vm, false);
651 } else {
652 return decodeVfpRegRegOp<VsqrtD>(
653 machInst, vd, vm, true);
654 }
655 }
656 case 0x2:
657 case 0x3:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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650 machInst, vd, vm, false);
651 } else {
652 return decodeVfpRegRegOp<VsqrtD>(
653 machInst, vd, vm, true);
654 }
655 }
656 case 0x2:
657 case 0x3:
658 // Between half and single precision.
659 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
658 {
659 const bool toHalf = bits(machInst, 16);
660 const bool top = bits(machInst, 7);
661 if (top) {
662 if (toHalf) {
663 return new VcvtFpSFpHT(machInst, vd, vm);
664 } else {
665 return new VcvtFpHTFpS(machInst, vd, vm);
666 }
667 } else {
668 if (toHalf) {
669 return new VcvtFpSFpHB(machInst, vd, vm);
670 } else {
671 return new VcvtFpHBFpS(machInst, vd, vm);
672 }
673 }
674 }
660 case 0x4:
661 if (single) {
662 if (e) {
663 return new VcmpeS(machInst, vd, vm);
664 } else {
665 return new VcmpS(machInst, vd, vm);
666 }
667 } else {

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676 if (single) {
677 if (e) {
678 return new VcmpeS(machInst, vd, vm);
679 } else {
680 return new VcmpS(machInst, vd, vm);
681 }
682 } else {

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