fp.isa (7379:92ef7238d230) fp.isa (7380:baee640ca6a4)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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720 if (half) {
721 return new VcvtUHFixedFpD(machInst, vd, vd, size);
722 } else {
723 return new VcvtUFixedFpD(machInst, vd, vd, size);
724 }
725 }
726 }
727 case 0xc:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 711 unchanged lines hidden (view full) ---

720 if (half) {
721 return new VcvtUHFixedFpD(machInst, vd, vd, size);
722 } else {
723 return new VcvtUFixedFpD(machInst, vd, vd, size);
724 }
725 }
726 }
727 case 0xc:
728 if (single) {
729 return new VcvtFpUIntS(machInst, vd, vm);
728 if (bits(machInst, 7) == 0) {
729 if (single) {
730 return new VcvtFpUIntSR(machInst, vd, vm);
731 } else {
732 vd = (IntRegIndex)(bits(machInst, 22) |
733 (bits(machInst, 15, 12) << 1));
734 return new VcvtFpUIntDR(machInst, vd, vm);
735 }
730 } else {
736 } else {
731 vd = (IntRegIndex)(bits(machInst, 22) |
732 (bits(machInst, 15, 12) << 1));
733 return new VcvtFpUIntD(machInst, vd, vm);
737 if (single) {
738 return new VcvtFpUIntS(machInst, vd, vm);
739 } else {
740 vd = (IntRegIndex)(bits(machInst, 22) |
741 (bits(machInst, 15, 12) << 1));
742 return new VcvtFpUIntD(machInst, vd, vm);
743 }
734 }
735 case 0xd:
744 }
745 case 0xd:
736 if (single) {
737 return new VcvtFpSIntS(machInst, vd, vm);
746 if (bits(machInst, 7) == 0) {
747 if (single) {
748 return new VcvtFpSIntSR(machInst, vd, vm);
749 } else {
750 vd = (IntRegIndex)(bits(machInst, 22) |
751 (bits(machInst, 15, 12) << 1));
752 return new VcvtFpSIntDR(machInst, vd, vm);
753 }
738 } else {
754 } else {
739 vd = (IntRegIndex)(bits(machInst, 22) |
740 (bits(machInst, 15, 12) << 1));
741 return new VcvtFpSIntD(machInst, vd, vm);
755 if (single) {
756 return new VcvtFpSIntS(machInst, vd, vm);
757 } else {
758 vd = (IntRegIndex)(bits(machInst, 22) |
759 (bits(machInst, 15, 12) << 1));
760 return new VcvtFpSIntD(machInst, vd, vm);
761 }
742 }
743 case 0xe:
744 {
745 const bool half = (bits(machInst, 7) == 0);
746 const uint32_t imm = bits(machInst, 5) |
747 (bits(machInst, 3, 0) << 1);
748 const uint32_t size =
749 (bits(machInst, 7) == 0 ? 16 : 32) - imm;

--- 48 unchanged lines hidden --- 		762 }
763 case 0xe:
764 {
765 const bool half = (bits(machInst, 7) == 0);
766 const uint32_t imm = bits(machInst, 5) |
767 (bits(machInst, 3, 0) << 1);
768 const uint32_t size =
769 (bits(machInst, 7) == 0 ? 16 : 32) - imm;

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