fp.isa (7374:9a80d013b955) fp.isa (7376:3b781776b2d9)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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499 (bits(machInst, 3, 0) << 1));
500 vn = (IntRegIndex)((bits(machInst, 7) << 5) |
501 (bits(machInst, 19, 16) << 1));
502 }
503 switch (opc1 & 0xb /* 1011 */) {
504 case 0x0:
505 if (bits(machInst, 6) == 0) {
506 if (single) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 490 unchanged lines hidden (view full) ---

499 (bits(machInst, 3, 0) << 1));
500 vn = (IntRegIndex)((bits(machInst, 7) << 5) |
501 (bits(machInst, 19, 16) << 1));
502 }
503 switch (opc1 & 0xb /* 1011 */) {
504 case 0x0:
505 if (bits(machInst, 6) == 0) {
506 if (single) {
507 return new VmlaS(machInst, vd, vn, vm);
507 return decodeVfpRegRegRegOp<VmlaS>(
508 machInst, vd, vn, vm, false);
508 } else {
509 } else {
509 return new VmlaD(machInst, vd, vn, vm);
510 return decodeVfpRegRegRegOp<VmlaD>(
511 machInst, vd, vn, vm, true);
510 }
511 } else {
512 if (single) {
512 }
513 } else {
514 if (single) {
513 return new VmlsS(machInst, vd, vn, vm);
515 return decodeVfpRegRegRegOp<VmlsS>(
516 machInst, vd, vn, vm, false);
514 } else {
517 } else {
515 return new VmlsD(machInst, vd, vn, vm);
518 return decodeVfpRegRegRegOp<VmlsD>(
519 machInst, vd, vn, vm, true);
516 }
517 }
518 case 0x1:
519 if (bits(machInst, 6) == 1) {
520 if (single) {
520 }
521 }
522 case 0x1:
523 if (bits(machInst, 6) == 1) {
524 if (single) {
521 return new VnmlaS(machInst, vd, vn, vm);
525 return decodeVfpRegRegRegOp<VnmlaS>(
526 machInst, vd, vn, vm, false);
522 } else {
527 } else {
523 return new VnmlaD(machInst, vd, vn, vm);
528 return decodeVfpRegRegRegOp<VnmlaD>(
529 machInst, vd, vn, vm, true);
524 }
525 } else {
526 if (single) {
530 }
531 } else {
532 if (single) {
527 return new VnmlsS(machInst, vd, vn, vm);
533 return decodeVfpRegRegRegOp<VnmlsS>(
534 machInst, vd, vn, vm, false);
528 } else {
535 } else {
529 return new VnmlsD(machInst, vd, vn, vm);
536 return decodeVfpRegRegRegOp<VnmlsD>(
537 machInst, vd, vn, vm, true);
530 }
531 }
532 case 0x2:
533 if ((opc3 & 0x1) == 0) {
534 if (single) {
538 }
539 }
540 case 0x2:
541 if ((opc3 & 0x1) == 0) {
542 if (single) {
535 return new VmulS(machInst, vd, vn, vm);
543 return decodeVfpRegRegRegOp<VmulS>(
544 machInst, vd, vn, vm, false);
536 } else {
545 } else {
537 return new VmulD(machInst, vd, vn, vm);
546 return decodeVfpRegRegRegOp<VmulD>(
547 machInst, vd, vn, vm, true);
538 }
539 } else {
540 if (single) {
548 }
549 } else {
550 if (single) {
541 return new VnmulS(machInst, vd, vn, vm);
551 return decodeVfpRegRegRegOp<VnmulS>(
552 machInst, vd, vn, vm, false);
542 } else {
553 } else {
543 return new VnmulD(machInst, vd, vn, vm);
554 return decodeVfpRegRegRegOp<VnmulD>(
555 machInst, vd, vn, vm, true);
544 }
545 }
546 case 0x3:
547 if ((opc3 & 0x1) == 0) {
548 if (single) {
556 }
557 }
558 case 0x3:
559 if ((opc3 & 0x1) == 0) {
560 if (single) {
549 return new VaddS(machInst, vd, vn, vm);
561 return decodeVfpRegRegRegOp<VaddS>(
562 machInst, vd, vn, vm, false);
550 } else {
563 } else {
551 return new VaddD(machInst, vd, vn, vm);
564 return decodeVfpRegRegRegOp<VaddD>(
565 machInst, vd, vn, vm, true);
552 }
553 } else {
554 if (single) {
566 }
567 } else {
568 if (single) {
555 return new VsubS(machInst, vd, vn, vm);
569 return decodeVfpRegRegRegOp<VsubS>(
570 machInst, vd, vn, vm, false);
556 } else {
571 } else {
557 return new VsubD(machInst, vd, vn, vm);
572 return decodeVfpRegRegRegOp<VsubD>(
573 machInst, vd, vn, vm, true);
558 }
559 }
560 case 0x8:
561 if ((opc3 & 0x1) == 0) {
562 if (single) {
574 }
575 }
576 case 0x8:
577 if ((opc3 & 0x1) == 0) {
578 if (single) {
563 return new VdivS(machInst, vd, vn, vm);
579 return decodeVfpRegRegRegOp<VdivS>(
580 machInst, vd, vn, vm, false);
564 } else {
581 } else {
565 return new VdivD(machInst, vd, vn, vm);
582 return decodeVfpRegRegRegOp<VdivD>(
583 machInst, vd, vn, vm, true);
566 }
567 }
568 break;
569 case 0xb:
570 if ((opc3 & 0x1) == 0) {
571 const uint32_t baseImm =
572 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
573 if (single) {
574 uint32_t imm = vfp_modified_imm(baseImm, false);
584 }
585 }
586 break;
587 case 0xb:
588 if ((opc3 & 0x1) == 0) {
589 const uint32_t baseImm =
590 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
591 if (single) {
592 uint32_t imm = vfp_modified_imm(baseImm, false);
575 return new VmovImmS(machInst, vd, imm);
593 return decodeVfpRegImmOp<VmovImmS>(
594 machInst, vd, imm, false);
576 } else {
577 uint64_t imm = vfp_modified_imm(baseImm, true);
595 } else {
596 uint64_t imm = vfp_modified_imm(baseImm, true);
578 return new VmovImmD(machInst, vd, imm);
597 return decodeVfpRegImmOp<VmovImmD>(
598 machInst, vd, imm, true);
579 }
580 }
581 switch (opc2) {
582 case 0x0:
583 if (opc3 == 1) {
584 if (single) {
599 }
600 }
601 switch (opc2) {
602 case 0x0:
603 if (opc3 == 1) {
604 if (single) {
585 return new VmovRegS(machInst, vd, vm);
605 return decodeVfpRegRegOp<VmovRegS>(
606 machInst, vd, vm, false);
586 } else {
607 } else {
587 return new VmovRegD(machInst, vd, vm);
608 return decodeVfpRegRegOp<VmovRegD>(
609 machInst, vd, vm, true);
588 }
589 } else {
590 if (single) {
610 }
611 } else {
612 if (single) {
591 return new VabsS(machInst, vd, vm);
613 return decodeVfpRegRegOp<VabsS>(
614 machInst, vd, vm, false);
592 } else {
615 } else {
593 return new VabsD(machInst, vd, vm);
616 return decodeVfpRegRegOp<VabsD>(
617 machInst, vd, vm, true);
594 }
595 }
596 case 0x1:
597 if (opc3 == 1) {
598 if (single) {
618 }
619 }
620 case 0x1:
621 if (opc3 == 1) {
622 if (single) {
599 return new VnegS(machInst, vd, vm);
623 return decodeVfpRegRegOp<VnegS>(
624 machInst, vd, vm, false);
600 } else {
625 } else {
601 return new VnegD(machInst, vd, vm);
626 return decodeVfpRegRegOp<VnegD>(
627 machInst, vd, vm, true);
602 }
603 } else {
604 if (single) {
628 }
629 } else {
630 if (single) {
605 return new VsqrtS(machInst, vd, vm);
631 return decodeVfpRegRegOp<VsqrtS>(
632 machInst, vd, vm, false);
606 } else {
633 } else {
607 return new VsqrtD(machInst, vd, vm);
634 return decodeVfpRegRegOp<VsqrtD>(
635 machInst, vd, vm, true);
608 }
609 }
610 case 0x2:
611 case 0x3:
612 // Between half and single precision.
613 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
614 case 0x4:
615 case 0x5:

--- 69 unchanged lines hidden --- 		636 }
637 }
638 case 0x2:
639 case 0x3:
640 // Between half and single precision.
641 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
642 case 0x4:
643 case 0x5:

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