fp.isa (7373:65786254fdd1) fp.isa (7374:9a80d013b955)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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611 case 0x3:
612 // Between half and single precision.
613 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
614 case 0x4:
615 case 0x5:
616 return new WarnUnimplemented("vcmp, vcmpe", machInst);
617 case 0x7:
618 if (opc3 == 0x3) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 602 unchanged lines hidden (view full) ---

611 case 0x3:
612 // Between half and single precision.
613 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
614 case 0x4:
615 case 0x5:
616 return new WarnUnimplemented("vcmp, vcmpe", machInst);
617 case 0x7:
618 if (opc3 == 0x3) {
619 // Between double and single precision.
620 return new WarnUnimplemented("vcvt", machInst);
619 if (single) {
620 vm = (IntRegIndex)(bits(machInst, 5) |
621 (bits(machInst, 3, 0) << 1));
622 return new VcvtFpSFpD(machInst, vd, vm);
623 } else {
624 vd = (IntRegIndex)(bits(machInst, 22) |
625 (bits(machInst, 15, 12) << 1));
626 return new VcvtFpDFpS(machInst, vd, vm);
627 }
621 }
622 break;
623 case 0x8:
624 if (bits(machInst, 7) == 0) {
625 if (single) {
626 return new VcvtUIntFpS(machInst, vd, vm);
627 } else {
628 vm = (IntRegIndex)(bits(machInst, 5) |

--- 49 unchanged lines hidden --- 		628 }
629 break;
630 case 0x8:
631 if (bits(machInst, 7) == 0) {
632 if (single) {
633 return new VcvtUIntFpS(machInst, vd, vm);
634 } else {
635 vm = (IntRegIndex)(bits(machInst, 5) |

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