fp.isa (7372:66dffab79795) fp.isa (7373:65786254fdd1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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616 return new WarnUnimplemented("vcmp, vcmpe", machInst);
617 case 0x7:
618 if (opc3 == 0x3) {
619 // Between double and single precision.
620 return new WarnUnimplemented("vcvt", machInst);
621 }
622 break;
623 case 0x8:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 607 unchanged lines hidden (view full) ---

616 return new WarnUnimplemented("vcmp, vcmpe", machInst);
617 case 0x7:
618 if (opc3 == 0x3) {
619 // Between double and single precision.
620 return new WarnUnimplemented("vcvt", machInst);
621 }
622 break;
623 case 0x8:
624 // Between FP and int.
625 return new WarnUnimplemented("vcvt, vcvtr", machInst);
624 if (bits(machInst, 7) == 0) {
625 if (single) {
626 return new VcvtUIntFpS(machInst, vd, vm);
627 } else {
628 vm = (IntRegIndex)(bits(machInst, 5) |
629 (bits(machInst, 3, 0) << 1));
630 return new VcvtUIntFpD(machInst, vd, vm);
631 }
632 } else {
633 if (single) {
634 return new VcvtSIntFpS(machInst, vd, vm);
635 } else {
636 vm = (IntRegIndex)(bits(machInst, 5) |
637 (bits(machInst, 3, 0) << 1));
638 return new VcvtSIntFpD(machInst, vd, vm);
639 }
640 }
626 case 0xa:
627 case 0xb:
628 // Between FP and fixed point.
629 return new WarnUnimplemented("vcvt", machInst);
630 case 0xc:
641 case 0xa:
642 case 0xb:
643 // Between FP and fixed point.
644 return new WarnUnimplemented("vcvt", machInst);
645 case 0xc:
646 if (single) {
647 return new VcvtFpUIntS(machInst, vd, vm);
648 } else {
649 vd = (IntRegIndex)(bits(machInst, 22) |
650 (bits(machInst, 15, 12) << 1));
651 return new VcvtFpUIntD(machInst, vd, vm);
652 }
631 case 0xd:
653 case 0xd:
632 // Between FP and int.
633 return new WarnUnimplemented("vcvt, vcvtr", machInst);
654 if (single) {
655 return new VcvtFpSIntS(machInst, vd, vm);
656 } else {
657 vd = (IntRegIndex)(bits(machInst, 22) |
658 (bits(machInst, 15, 12) << 1));
659 return new VcvtFpSIntD(machInst, vd, vm);
660 }
634 case 0xe:
635 case 0xf:
636 // Between FP and fixed point.
637 return new WarnUnimplemented("vcvt", machInst);
638 }
639 break;
640 }
641 return new Unknown(machInst);
642 }
643 '''
644}};
645
646def format VfpData() {{
647 decode_block = '''
648 return decodeVfpData(machInst);
649 '''
650}};
661 case 0xe:
662 case 0xf:
663 // Between FP and fixed point.
664 return new WarnUnimplemented("vcvt", machInst);
665 }
666 break;
667 }
668 return new Unknown(machInst);
669 }
670 '''
671}};
672
673def format VfpData() {{
674 decode_block = '''
675 return decodeVfpData(machInst);
676 '''
677}};