fp.isa (7370:6fa1e296585d) fp.isa (7371:83612101a826)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 510 unchanged lines hidden (view full) ---

519 vm = (bits(machInst, 5) << 5) |
520 (bits(machInst, 3, 0) << 1);
521 vn = (bits(machInst, 7) << 5) |
522 (bits(machInst, 19, 16) << 1);
523 return new VmlsD(machInst, (IntRegIndex)vd,
524 (IntRegIndex)vn, (IntRegIndex)vm);
525 }
526 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 510 unchanged lines hidden (view full) ---

519 vm = (bits(machInst, 5) << 5) |
520 (bits(machInst, 3, 0) << 1);
521 vn = (bits(machInst, 7) << 5) |
522 (bits(machInst, 19, 16) << 1);
523 return new VmlsD(machInst, (IntRegIndex)vd,
524 (IntRegIndex)vn, (IntRegIndex)vm);
525 }
526 }
527 case 0x1:
528 if (bits(machInst, 6) == 1) {
529 uint32_t vd;
530 uint32_t vm;
531 uint32_t vn;
532 if (bits(machInst, 8) == 0) {
533 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
534 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
535 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
536 return new VnmlaS(machInst, (IntRegIndex)vd,
537 (IntRegIndex)vn, (IntRegIndex)vm);
538 } else {
539 vd = (bits(machInst, 22) << 5) |
540 (bits(machInst, 15, 12) << 1);
541 vm = (bits(machInst, 5) << 5) |
542 (bits(machInst, 3, 0) << 1);
543 vn = (bits(machInst, 7) << 5) |
544 (bits(machInst, 19, 16) << 1);
545 return new VnmlaD(machInst, (IntRegIndex)vd,
546 (IntRegIndex)vn, (IntRegIndex)vm);
547 }
548 } else {
549 uint32_t vd;
550 uint32_t vm;
551 uint32_t vn;
552 if (bits(machInst, 8) == 0) {
553 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
554 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
555 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
556 return new VnmlsS(machInst, (IntRegIndex)vd,
557 (IntRegIndex)vn, (IntRegIndex)vm);
558 } else {
559 vd = (bits(machInst, 22) << 5) |
560 (bits(machInst, 15, 12) << 1);
561 vm = (bits(machInst, 5) << 5) |
562 (bits(machInst, 3, 0) << 1);
563 vn = (bits(machInst, 7) << 5) |
564 (bits(machInst, 19, 16) << 1);
565 return new VnmlsD(machInst, (IntRegIndex)vd,
566 (IntRegIndex)vn, (IntRegIndex)vm);
567 }
568 }
527 case 0x2:
528 if ((opc3 & 0x1) == 0) {
529 uint32_t vd;
530 uint32_t vm;
531 uint32_t vn;
532 if (bits(machInst, 8) == 0) {
533 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
534 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);

--- 5 unchanged lines hidden (view full) ---

540 (bits(machInst, 15, 12) << 1);
541 vm = (bits(machInst, 5) << 5) |
542 (bits(machInst, 3, 0) << 1);
543 vn = (bits(machInst, 7) << 5) |
544 (bits(machInst, 19, 16) << 1);
545 return new VmulD(machInst, (IntRegIndex)vd,
546 (IntRegIndex)vn, (IntRegIndex)vm);
547 }
569 case 0x2:
570 if ((opc3 & 0x1) == 0) {
571 uint32_t vd;
572 uint32_t vm;
573 uint32_t vn;
574 if (bits(machInst, 8) == 0) {
575 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
576 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);

--- 5 unchanged lines hidden (view full) ---

582 (bits(machInst, 15, 12) << 1);
583 vm = (bits(machInst, 5) << 5) |
584 (bits(machInst, 3, 0) << 1);
585 vn = (bits(machInst, 7) << 5) |
586 (bits(machInst, 19, 16) << 1);
587 return new VmulD(machInst, (IntRegIndex)vd,
588 (IntRegIndex)vn, (IntRegIndex)vm);
589 }
590 } else {
591 uint32_t vd;
592 uint32_t vm;
593 uint32_t vn;
594 if (bits(machInst, 8) == 0) {
595 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
596 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
597 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
598 return new VnmulS(machInst, (IntRegIndex)vd,
599 (IntRegIndex)vn, (IntRegIndex)vm);
600 } else {
601 vd = (bits(machInst, 22) << 5) |
602 (bits(machInst, 15, 12) << 1);
603 vm = (bits(machInst, 5) << 5) |
604 (bits(machInst, 3, 0) << 1);
605 vn = (bits(machInst, 7) << 5) |
606 (bits(machInst, 19, 16) << 1);
607 return new VnmulD(machInst, (IntRegIndex)vd,
608 (IntRegIndex)vn, (IntRegIndex)vm);
609 }
548 }
610 }
549 case 0x1:
550 return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst);
551 case 0x3:
552 if ((opc3 & 0x1) == 0) {
553 uint32_t vd;
554 uint32_t vm;
555 uint32_t vn;
556 if (bits(machInst, 8) == 0) {
557 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
558 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);

--- 183 unchanged lines hidden --- 		611 case 0x3:
612 if ((opc3 & 0x1) == 0) {
613 uint32_t vd;
614 uint32_t vm;
615 uint32_t vn;
616 if (bits(machInst, 8) == 0) {
617 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
618 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);

--- 183 unchanged lines hidden ---