fp.isa (7368:3053e3587124) fp.isa (7369:f71b906540cf)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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547 vn = (bits(machInst, 7) << 5) |
548 (bits(machInst, 19, 16) << 1);
549 return new VsubD(machInst, (IntRegIndex)vd,
550 (IntRegIndex)vn, (IntRegIndex)vm);
551 }
552 }
553 case 0x8:
554 if ((opc3 & 0x1) == 0) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 538 unchanged lines hidden (view full) ---

547 vn = (bits(machInst, 7) << 5) |
548 (bits(machInst, 19, 16) << 1);
549 return new VsubD(machInst, (IntRegIndex)vd,
550 (IntRegIndex)vn, (IntRegIndex)vm);
551 }
552 }
553 case 0x8:
554 if ((opc3 & 0x1) == 0) {
555 return new WarnUnimplemented("vdiv", machInst);
555 uint32_t vd;
556 uint32_t vm;
557 uint32_t vn;
558 if (bits(machInst, 8) == 0) {
559 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
560 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
561 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
562 return new VdivS(machInst, (IntRegIndex)vd,
563 (IntRegIndex)vn, (IntRegIndex)vm);
564 } else {
565 vd = (bits(machInst, 22) << 5) |
566 (bits(machInst, 15, 12) << 1);
567 vm = (bits(machInst, 5) << 5) |
568 (bits(machInst, 3, 0) << 1);
569 vn = (bits(machInst, 7) << 5) |
570 (bits(machInst, 19, 16) << 1);
571 return new VdivD(machInst, (IntRegIndex)vd,
572 (IntRegIndex)vn, (IntRegIndex)vm);
573 }
556 }
557 break;
558 case 0xb:
559 if ((opc3 & 0x1) == 0) {
560 uint32_t vd;
561 const uint32_t baseImm =
562 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
563 if (bits(machInst, 8) == 0) {

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619 vd = (bits(machInst, 22) << 5) |
620 (bits(machInst, 15, 12) << 1);
621 vm = (bits(machInst, 5) << 5) |
622 (bits(machInst, 3, 0) << 1);
623 return new VnegD(machInst,
624 (IntRegIndex)vd, (IntRegIndex)vm);
625 }
626 } else {
574 }
575 break;
576 case 0xb:
577 if ((opc3 & 0x1) == 0) {
578 uint32_t vd;
579 const uint32_t baseImm =
580 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
581 if (bits(machInst, 8) == 0) {

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637 vd = (bits(machInst, 22) << 5) |
638 (bits(machInst, 15, 12) << 1);
639 vm = (bits(machInst, 5) << 5) |
640 (bits(machInst, 3, 0) << 1);
641 return new VnegD(machInst,
642 (IntRegIndex)vd, (IntRegIndex)vm);
643 }
644 } else {
627 return new WarnUnimplemented("vsqrt", machInst);
645 uint32_t vd;
646 uint32_t vm;
647 if (bits(machInst, 8) == 0) {
648 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
649 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
650 return new VsqrtS(machInst,
651 (IntRegIndex)vd, (IntRegIndex)vm);
652 } else {
653 vd = (bits(machInst, 22) << 5) |
654 (bits(machInst, 15, 12) << 1);
655 vm = (bits(machInst, 5) << 5) |
656 (bits(machInst, 3, 0) << 1);
657 return new VsqrtD(machInst,
658 (IntRegIndex)vd, (IntRegIndex)vm);
659 }
628 }
629 case 0x2:
630 case 0x3:
631 // Between half and single precision.
632 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
633 case 0x4:
634 case 0x5:
635 return new WarnUnimplemented("vcmp, vcmpe", machInst);

--- 34 unchanged lines hidden --- 		660 }
661 case 0x2:
662 case 0x3:
663 // Between half and single precision.
664 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
665 case 0x4:
666 case 0x5:
667 return new WarnUnimplemented("vcmp, vcmpe", machInst);

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