fp.isa (7363:3b3b3325140c) fp.isa (7364:9d34477e6adb)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 472 unchanged lines hidden (view full) ---

481 const uint32_t opc2 = bits(machInst, 19, 16);
482 const uint32_t opc3 = bits(machInst, 7, 6);
483 //const uint32_t opc4 = bits(machInst, 3, 0);
484 switch (opc1 & 0xb /* 1011 */) {
485 case 0x0:
486 return new WarnUnimplemented("vmla, vmls", machInst);
487 case 0x2:
488 if ((opc3 & 0x1) == 0) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 472 unchanged lines hidden (view full) ---

481 const uint32_t opc2 = bits(machInst, 19, 16);
482 const uint32_t opc3 = bits(machInst, 7, 6);
483 //const uint32_t opc4 = bits(machInst, 3, 0);
484 switch (opc1 & 0xb /* 1011 */) {
485 case 0x0:
486 return new WarnUnimplemented("vmla, vmls", machInst);
487 case 0x2:
488 if ((opc3 & 0x1) == 0) {
489 return new WarnUnimplemented("vmul", machInst);
489 uint32_t vd;
490 uint32_t vm;
491 uint32_t vn;
492 if (bits(machInst, 8) == 0) {
493 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
494 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
495 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
496 return new VmulS(machInst, (IntRegIndex)vd,
497 (IntRegIndex)vn, (IntRegIndex)vm);
498 } else {
499 vd = (bits(machInst, 22) << 5) |
500 (bits(machInst, 15, 12) << 1);
501 vm = (bits(machInst, 5) << 5) |
502 (bits(machInst, 3, 0) << 1);
503 vn = (bits(machInst, 7) << 5) |
504 (bits(machInst, 19, 16) << 1);
505 return new VmulD(machInst, (IntRegIndex)vd,
506 (IntRegIndex)vn, (IntRegIndex)vm);
507 }
490 }
491 case 0x1:
492 return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst);
493 case 0x3:
494 if ((opc3 & 0x1) == 0) {
495 return new WarnUnimplemented("vadd", machInst);
496 } else {
497 return new WarnUnimplemented("vsub", machInst);

--- 90 unchanged lines hidden --- 		508 }
509 case 0x1:
510 return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst);
511 case 0x3:
512 if ((opc3 & 0x1) == 0) {
513 return new WarnUnimplemented("vadd", machInst);
514 } else {
515 return new WarnUnimplemented("vsub", machInst);

--- 90 unchanged lines hidden ---