fp.isa (6724:70129fdded75) | fp.isa (7178:7f0ac1abc621) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// |
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3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright --- 120 unchanged lines hidden (view full) --- 131 "predicate_test": predicateTest}, 132 flags) 133 header_output = BasicDeclare.subst(iop) 134 decoder_output = BasicConstructor.subst(iop) 135 decode_block = BasicDecode.subst(iop) 136 exec_output = FPAExecute.subst(iop) 137}}; 138 | 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright --- 120 unchanged lines hidden (view full) --- 143 "predicate_test": predicateTest}, 144 flags) 145 header_output = BasicDeclare.subst(iop) 146 decoder_output = BasicConstructor.subst(iop) 147 decode_block = BasicDecode.subst(iop) 148 exec_output = FPAExecute.subst(iop) 149}}; 150 |
139 | 151def format ExtensionRegLoadStore() {{ 152 decode_block = ''' 153 { 154 const uint32_t opcode = bits(machInst, 24, 20); 155 const uint32_t offset = bits(machInst, 7, 0); 156 const bool single = bits(machInst, 22); 157 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 158 RegIndex vd; 159 if (single) { 160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 161 bits(machInst, 22)); 162 } else { 163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 164 (bits(machInst, 22) << 5)); 165 } 166 switch (bits(opcode, 4, 3)) { 167 case 0x0: 168 if (bits(opcode, 4, 1) == 0x2) { 169 return new WarnUnimplemented("core-to-extension-transfer", 170 machInst); 171 } 172 break; 173 case 0x1: 174 switch (bits(opcode, 1, 0)) { 175 case 0x0: 176 return new VLdmStm(machInst, rn, vd, single, 177 true, false, false, offset); 178 case 0x1: 179 return new VLdmStm(machInst, rn, vd, single, 180 true, false, true, offset); 181 case 0x2: 182 return new VLdmStm(machInst, rn, vd, single, 183 true, true, false, offset); 184 case 0x3: 185 // If rn == sp, then this is called vpop. 186 return new VLdmStm(machInst, rn, vd, single, 187 true, true, true, offset); 188 } 189 case 0x2: 190 if (bits(opcode, 1, 0) == 0x2) { 191 // If rn == sp, then this is called vpush. 192 return new VLdmStm(machInst, rn, vd, single, 193 false, true, false, offset); 194 } else if (bits(opcode, 1, 0) == 0x3) { 195 return new VLdmStm(machInst, rn, vd, single, 196 false, true, true, offset); 197 } 198 // Fall through on purpose 199 case 0x3: 200 if (bits(opcode, 1, 0) == 0x0) { 201 return new WarnUnimplemented("vstr", machInst); 202 } else if (bits(opcode, 1, 0) == 0x1) { 203 return new WarnUnimplemented("vldr", machInst); 204 } 205 } 206 return new Unknown(machInst); 207 } 208 ''' 209}}; |